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Table of contents

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First part of this two-book series
Basic Computer Architecture

old book

Class Notes/Draft Chapters

[Note that all the copyrights belong to the publisher, McGrawHill]. These class notes/draft chapters are early
versions of the chapters that ultimately went to print after modifications.
These materials can only be viewed online; they cannot be downloaded.
If you wish to procure a pdf copy, then please access McGrawHill's digital library.

Individual chapters:
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Chapter 1: Introduction
Chapter 8: The On-Chip Network
Chapter 2: Out-of-order Pipelines
Chapter 9: Multicore Systems
Chapter 3: The Fetch and Decode Stages
Chapter 10: Main Memory
Chapter 4: The Issue, Execute, and Commit Stages
Chapter 11: Power and Temperature
Chapter 5: Alternative Approaches to Issue and Commit
Chapter 12: Reliability
Chapter 6: Graphics Processors
Chapter 13: Secure Processor Architectures
Chapter 7: Caches
Chapter 14: Architectures for ML accelerators
Appendices: ISA, Tejas simulator, Intel, AMD,
and Qualcomm processors

Bibliography
 

Slides and YouTube Videos


Slides
YouTube Videos (click the  YouTube link link)
Chapter 1: Introduction
1. Introduction YouTube link
Chapter 2: Out-of-order pipelines
1. Summary of in-order pipelining YouTube link
2. Motivation for out-of-order pipelining YouTube link
3. Register renaming and precise exceptions  YouTube link
Chatper 3: The fetch and decode stages
1. Fetch logic. YouTube link
2. Branch prediction YouTube link
3. Decode stage YouTube link

Notes on operating systems: [pdf]
Chapter 4: Issue, execute, commit
1. Instruction renaming YouTube link
2. Wakeup, select, and broadcast YouTube link
3. Load store queue YouTube link
4. Instruction commit YouTube link
Chapter 5: Alternative approaches to issue and commit
1. Aggressive speculation YouTube link
2. Replay schemes YouTube link 
3. Compiler based techniques YouTube link 
4. VLIW and EPIC processors YouTube link
Chapter 6: Graphics Processors
1. Traditional graphics pipeline YouTube link
2. The CUDA programming language YouTube link
3. Design of GPGPUs YouTube link
Chapter 7: Caches
1. Overview of caches YouTube link 
2. Cache optimizations and virtual memory YouTube link 
3. SRAM and CAM arrays YouTube link 
4. Cacti tool, Elmore delay YouTube link
5. Advanced cache optimizations YouTube link 
6. Trace caches, instruction, and data prefetching YouTube link 
Chapter 8: NoC
... Coming soon ...

Chapter 9: Multicore Systems
1. Parallel programming and hardware threads YouTube link
2. Theoretical foundations YouTube link
3. Sequential consistency, PLSC, and coherence YouTube link 
4. Execution witnesses, access graphs, causal graphs YouTube link
5. Cache coherence: snoopy and directory protocols YouTube link 
6. Advanced directory protocols and atomic operations  YouTube link
7. Memory models and data races YouTube link 
8. Methods to detect races YouTube link
9. Transactional memory YouTube link
Chapter 10: Main Memory ... Coming soon ....
Chapter 11: Power and Temperature ... Coming soon ....
Chapter 12: Reliability ... Coming soon ....
Chapter 13: Secure Architectures

1. Cryptographic fundamentals and encryption YouTube link
2. Hashing and secure processors YouTube link
3. Side channel attacks [... coming soon ...]

Chapter 14: Architectures for ML
... Coming soon ....

Software

Tejas Architecture Simulator --  Can be used to simulate the behaviour of simple and complex multicore
processors including their pipelines, memory hierarchies, and NOCs. The simulator can also run in parallel,
simulate GPUs, and simulate energy consumption. The latest version supports the ARM and RISC-V
ISAs. Written by the SRISHTI group

Cite the book

@book{advbook,
author = {Smruti R. Sarangi},
title = {Advanced Computer Architecture},
date = {21st July 2021},
edition = {1st edition},
publisher={McGrawHill},
isbn={9390727499} }