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Professional Experience


Position
 Period
 		Work
 Place
Research Scholar Since August 2008 Architecture exploration of  FPGA based
accelerators for Bioinformatics applications.		 Indian Institute of Technology Delhi,  India.
www.iitd.ac.in
Research Intern November-2011 to May-2012 (6 months) Accelerating de-Novo Genome Assembly using FPGAs. Symbiose Group, IRISA,
Rennes-Cedex, France
www.irisa.fr/symbiose/
Research Intern December 2007 – May 2008 (6 months) Reconfigurable computing using Leon soft-core processor on Xilinx FPGA. Centre for High Performance Embedded Systems, NTU, Singapore
www.chipes.ntu.edu.sg
Research Intern August 2007 – October 2007
 (3 months) 		UNISIM (Simulator for Multiprocessors). Alchemy group,
INRIA Futurs, France
www.inria.fr
Software Engineer June 2006 – August 2007 (1 year 3 months) EDA Tool development for QuickLogic FPGAs QuickLogic India Pvt Ltd., Bangalore, India. www.quicklogic.com
Program Analyst Trainee May 2004 – October 2004 (6 months) Enhancement of software for IBM POS machines.
 Cognizant Technology Solutions India Pvt. Ltd., Chennai, India
www.cognizant.com


Education

Master of Science (M.S) in VLSI_CAD (2005-2007) 
Manipal University, Manipal, India

Bachelor of Engineering (B.E) in Electronics and communication engineering (1999-2003)
Bapuji Institute of Engineering & Technology
Visvesvaraya Technological University, Belgaum, India

Specialization

System level design and modeling, Hardware-software codesign, Computer Architecture, FPGA, Digital Electronics, Hardware Accelerators

Publication


1. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier: “Hardware Acceleration of De Novo Genome Assembly”, Integration, the VLSI Journal, (submitted Aug-2013)

2. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan: "Accelerating Genome Assembly using Hard Embedded Blocks in FPGAs." IEEE 27th International Conference on VLSI Design: 306-311

3. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier: "FAssem: FPGA Based Acceleration of De Novo Genome Assembly." IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines 2013: 173-176

4. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan: "Accelerating 3D-FFT using Hard Embedded Blocks in FPGAs." IEEE 26th International Conference on VLSI Design: 92-97

References

Prof. M. Balakrishnan
Department of Computer Science and Engineering,
Indian Institute of Technology Delhi,
New-Delhi 110016
mbala at cse.iitd.ac.in

Prof. Kolin Paul
Department of Computer Science and Engineering,
Indian Institute of Technology Delhi,
New-Delhi 110016
kolin at cse.iitd.ac.in

Dominique Lavenier
CNRS Research Director and GenScale team leader
IRISA / INRIA
Campus de Beaulieu
35042 Rennes cedex France
lavenier at irisa.fr