Recent Publications

 

  1. G Ananthanarayanan, SR Sarangi, M Balakrishnan, “Leakage Power Aware Task Assignment Algorithms for Multicore Platforms”, VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on VLSI, 11-13 July, Pittsburg, USA, 607-612

  2. Kunal Kwatra, Renu Kaushik, Lipika Vidawat, Vibha Choudhary, Mayank Aamseek, Kameshwar Chesetti, M. Balakrishnan, “Converting Mathematics Textbook to Tactile Form: Process and Experiences”, DEIMS 2016, Kanagawa , Japan, 4-6 Feb 2016

  3. Manish Kumar Jaiswal, B. Sharat Chandra Verma, Hayden K.-H. So, M. Balakrishnan, Kolin Paul, Ray C.C. Cheung, “Configurable Architectures for Multi-Mode Floating Point Adders”, IEEE Trans. On Circuits and Systems I, Vol 62(8), 2079-2090, 2015

  4. Pulkit Sapra, Ankit Kumar Parsurampuria, Dhruv Gupta, Suman Muralikrishnan, Mayank Raj, Akash Anand, Vinit Darda, Rohan Paul, M Balakrishnan and P.V.M. Rao, “A Compliant Mechanism Design for Refreshable Braille Display Using Shape Memory Alloy”, ASME – MESA 2015, 2-5 Aug 2015, Boston, USA

  5. Dheeraj Mehra, Deepak Gupta, Vishwarath.T, Neil Shah, Piyush Chanana, Siddharth, Rohan Paul, BalaKrishnan M and PVM Rao, "Bus Identification System for Visually Impaired: Evaluation and learning from field trials", TRANSED 2015, 29-31 July 2015, Lisbon, Portugal

  6. Rajeswari Devadoss, Kolin Paul and M Balakrishnan, "MajSynth : An n-input Majority Algebra based Logic Synthesis Tool for Quantum-dot Cellular Automata", 22nd Intl. Workshop on Logic Synthesis, 12-13 June 2015, Mountain View, California

  7. Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul, "Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform", ARC 2015, 13-17 April, 2015, Bochum, Germany, pp. 373-382

  8. Arun Kumar Parakh, M. Balakrishnan and Kolin Paul, "Improving Map-Reduce for GPUs with cache", Int. J. High Performance Systems Architecture, Vol. 5, No. 3, 2015, pp. 166-177

  9. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, "Series Expansion based Efficient Architectures for Double Precision Floating Point Division", Circuits Systems and Signal Processing, vol. 33, No. 11, 2014, pp. 3499-3526

  10. Ankit Kumar Parsurampuria, Dhruv Gupta, Pulkit Sapra, Mayank Raj, Akash Anand, Vinit Darda, Rohan Paul, M. Balakrishnan, P.V.M. Rao, "A Compliant Mechanism Design for Refreshable Braille Display Using Shape Memory Alloy", ASME/IEEE MESA 2014, Sep. 10-12, Senigallia, Italy

  11. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, "High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs" DSD 2014, 27-29 Aug., Verona, Italy, pp. 66-73

  12. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, "Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder", IEEE Trans. on Circuits and Systems Vol. 61-II, No. 7, 2014, pp. 521-525

  13. Mrinal Mech, Kunal Kwatra, Supriya Das, Piyush Chanana, Rohan Paul, M. Balakrishnan, "Edutactile - A Tool for Rapid Generation of Accurate Guideline-Compliant Tactile Graphics for Science and Mathematics.", ICCHP (2), 7-11 July, 2014, Paris, France, pp. 34-41

  14. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, "Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division", ISVLSI 2014, 2-9 July 2014, Tampa, Florida, pp. 332-33

  15. M. Balakrishnan, "Design of an Affordable and Flexible Braille Tutor", Blindness, Technology, and Multimodal Reading Conference, London, 27-28 June 2014

  16. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, "Series Expansion based Efficient Architectures for Double Precision Floating Point Division", CSSP, Springer Science, Appeared online May 15, 2014, DOI 10.1007/s00034-014-9811-8

  17. Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan, "Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array", (Poster paper) FCCM 2014, 11-13 May, Boston, pp 33

  18. Smruti R. Sarangi, Gayathri Ananthanarayanan, and M. Balakrishnan, "LightSim : A Leakage Aware Ultrafast Temperature Simulator", 19th ASP-DAC, 20-23 Jan 2014, Singapore, pp. 855-860

  19. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, "Accelerating Genome Assembly using Hard Embedded Blocks in FPGAs.", IEEE 27th International Conference on VLSI Design, 5-9 Jan 2014, Mumbai, pp. 306-311

  20. Dhruv Jain, Akhil Jain, Rohan Paul, Akhila Komarika and M. Balakrishnan, "A path-guided audio based indoor navigation system for persons with visual impairment" ASSETS 2013, 21-23 Oct Bellevue, Washington, pp. 33

  21. Anshul Singhal, Pranay Jain, Piyush Chanana, Dhruv Jain, Rohan Paul, M. Balakrishnan and P. V. M. Rao, "Application of Shape Memory Alloy (SMA) Based Actuation for Refreshable Display of Braille", ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications (MESA2013), Portland, Oregon, August 4-7, 2013, pp. ??

  22. Kolin Paul, M. Balakrishnan and Mansureh Shahraki Moghaddam, "Design and Implementation of high Performance Architectures with Partially Reconfigurable CGRAs", the 20th Reconfigurable Architectures Workshop, RAW 2013, Boston, May 2013

  23. Gayathri Ananthanarayanan, Geetika Malhotra, M. Balakrishnan, and Smruti R. Sarangi, "Amdahl's Law in the Era of Process Variation", Vol. 4, No. 4, 2013, International Journal of High Performance Systems Architecture (IJHPSA), pp. 218-230

  24. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier, "FAssem : FPGA based Acceleration of De Novo Genome Assembly" (short paper), FCCM 2013, April 2013, Seattle, USA

  25. Arun Parakh, M. Balakrishnan, Kolin Paul, "Performance Enhancemnt of Map-Reduce Framework on GPU", The 11th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2013, February 11-13, 2013, Innsbruck, Austria

  26. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, "Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs" 26th Proceedings of the International Conference on VLSI Design,, Pune, India, Jan 2013, pp. 92-97

  27. Arun Parakh, M. Balakrishnan, Kolin Paul, "Performance Estimation of GPUs with Cache", IPDPS Workshops 2012, Shanghai, China May 2012, pp. 2384-2393

  28. Sonali Chouhan, M. Balakrishnan, Ranjan Bose, "System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation", IEEE Trans. on CAD of Integrated Circuits and Systemsi, Vol. 31, No.4, 2012, pp. 586-596

  29. Rajeswari Devadoss, Kolin Paul, M. Balakrishnan, "Architecture and tools for programmable QCA", FPT 2011, Dec. 2011, Delhi, pp. 1-4

  30. P Panda, M Balakrishnan and A. Vishnoi, "Compressing Cache State for Post-Silicon Processor Debug", IEEE Transactions on Computers, Vol. 60, No. 4, April 2011, pp 484-497

  31. Rajeswari Devadoss, Kolin Paul, M. Balakrishnan, "p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata", JETC, Vol. 7, No. 3, 2011, Article No. 13

  32. R. Devadoss, K. Paul, M. Balakrishnan, "A Tiled Programmable Fabric using QCA", FPT 2010, Beijing, Dec. 2010, pp. 9-16

  33. Preeti Ranjan Panda, Anant Vishnoi and M. Balakrishnan, “Enhancing post-silicon processor debug with Incremental Cache state Dumping”, IEEE VLSI-SOC, Madrid, Spain, September 2010, pp. 55-60

  34. R. Devadoss, K. Paul, M. Balakrishnan, "Clocking-based Coplanar Wire Crossing Scheme for QCA", 23rd Proceedings of the International Conference on VLSI Design, Bengaluru, India, Jan. 2010, pp. 339-344

  35. R. Devadoss, K. Paul, M. Balakrishnan, “Coplanar QCA crossovers”, Electronics Letters, Volume 45,  Issue 24,  November 19 2009, pp.1234 – 1235

  36. Sonali Chouhan, Ranjan Bose, M. Balakrishnan, “Integrated Energy Analysis of Error Correcting Codes and Modulation for Energy Efficient Wireless Sensor Nodes”, IEEE Transactions on Wireless Communications, Volume 8,  Issue 10,  October 2009, pp. 5348 – 5355

  37. R. Devadoss, K. Paul, M. Balakrishnan, "Clocking-based Coplanar Wire Crossing Scheme for QCA", 1st International Workshop on Quantum-dot Cellular Automata, UBC, Vancouver, Canada, Aug. 2009.

  38. Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan, “Online Cache State Dumping for Processor Debug”. DAC 2009, pp. 358-363, Aug. 2009

  39. Sonali Chouhan, M. Balakrishnan, Ranjan Bose, “An Experimental Validation of System Level Design Space Exploration Methodology for Energy Efficient Sensor Nodes”, ISLPED 2009,  pp. 355-358, Aug. 2009

  40. Sonali Chouhan, Ranjan Bose, M. Balakrishnan, “A Framework for Energy Consumption Based Design Space Exploration for Wireless Sensor Nodes”, IEEE TCAD, Volume 28,  Issue 7,  July 2009, pp. 1017 – 1024

  41. Anant Vishnoi, Preeti Ranjan Panda and  M. Balakrishnan,  “Cache Aware Compression for Processor Debug Support”   Design Automation and Test in Europe (DATE), 20-24 April, Nice, France, pp. 208-213, April 2009

  42. Sahu, M. Balakrishnan and Preeti Ranjan Panda, “A Generic Platform for Estimation of Multi-threaded Program Performance on Heterogeneous Multiprocessor”, Design Automation and Test in Europe (DATE) 20-24 April, Nice, France, pp. 1018-1023, April 2009

  43. Kolin Paul,  M. Balakrishnan, Advait Jain, Pulkit Gambhir and Priyanka Jindal, “FPGA Accelerator for Protein Structure Prediction Algorithms” SPL 2009, Sao Carlos, Brazil, 1-3 April 2009, pp. 123-128