Complete List of Publications

 

  1. G Ananthanarayanan, SR Sarangi, M Balakrishnan, “Leakage Power Aware Task Assignment Algorithms for Multicore Platforms”, VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on VLSI, 11-13 July, Pittsburg, USA, 607-612

  2. A Gulati, M Balakrishnan, SRN Reddy, “An Audio Tactile Storybook for Visually Impaired Children” National Conference on Product Design, NCPD 2016, Bangaluru, July 2016

  3. Kunal Kwatra, Renu Kaushik, Lipika Vidawat, Vibha Choudhary, Mayank Aamseek, Kameshwar Chesetti, M. Balakrishnan, “Converting Mathematics Textbook to Tactile Form: Process and Experiences”, DEIMS 2016, Kanagawa , Japan, 4-6 Feb 2016

  4. Siddhartha Gupta, Manshul V Belani, Dinesh Kaushal, M. Balakrishnan, “Microsoft Excel ChartsTMAccessibility: An Affordable and Effective Solution”, DEIMS 2016, Kanagawa , Japan, 4-6 Feb 2016

  5. Manish Kumar Jaiswal, B. Sharat Chandra Verma, Hayden K.-H. So, M. Balakrishnan, Kolin Paul, Ray C.C. Cheung, “Configurable Architectures for Multi-Mode Floating Point Adders”, IEEE Trans. On Circuits and Systems I, Vol 62(8), 2079-2090, 2015

  6. Pulkit Sapra, Ankit Kumar Parsurampuria, Dhruv Gupta, Suman Muralikrishnan, Mayank Raj, Akash Anand, Vinit Darda, Rohan Paul, M Balakrishnan and P.V.M. Rao, “A Compliant Mechanism Design for Refreshable Braille Display Using Shape Memory Alloy”, ASME – MESA 2015, 2-5 Aug 2015, Boston, USA

  7. Dheeraj Mehra, Deepak Gupta, Vishwarath.T, Neil Shah, Piyush Chanana, Siddharth, Rohan Paul, BalaKrishnan M and PVM Rao, "Bus Identification System for Visually Impaired: Evaluation and learning from field trials", TRANSED 2015, 29-31 July 2015, Lisbon, Portugal

  8. Rajeswari Devadoss, Kolin Paul and M Balakrishnan, "MajSynth : An n-input Majority Algebra based Logic Synthesis Tool for Quantum-dot Cellular Automata", 22nd Intl. Workshop on Logic Synthesis, 12-13 June 2015, Mountain View, California

  9. Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul, "Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform", ARC 2015, 13-17 April, 2015, Bochum, Germany, pp. 373-382

  10. Arun Kumar Parakh, M. Balakrishnan and Kolin Paul, "Improving Map-Reduce for GPUs with cache", Int. J. High Performance Systems Architecture, Vol. 5, No. 3, 2015, pp. 166-177

  11. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, "Series Expansion based Efficient Architectures for Double Precision Floating Point Division", Circuits Systems and Signal Processing, vol. 33, No. 11, 2014, pp. 3499-3526

  12. Ankit Kumar Parsurampuria, Dhruv Gupta, Pulkit Sapra, Mayank Raj, Akash Anand, Vinit Darda, Rohan Paul, M. Balakrishnan, P.V.M. Rao, "A Compliant Mechanism Design for Refreshable Braille Display Using Shape Memory Alloy", ASME/IEEE MESA 2014, Sep. 10-12, Senigallia, Italy

  13. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, "High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs" DSD 2014, 27-29 Aug., Verona, Italy, pp. 66-73

  14. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, "Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder", IEEE Trans. on Circuits and Systems Vol. 61-II, No. 7, 2014, pp. 521-525

  15. Mrinal Mech, Kunal Kwatra, Supriya Das, Piyush Chanana, Rohan Paul, M. Balakrishnan, "Edutactile - A Tool for Rapid Generation of Accurate Guideline-Compliant Tactile Graphics for Science and Mathematics.", ICCHP (2), 7-11 July, 2014, Paris, France, pp. 34-41

  16. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, "Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division", ISVLSI 2014, 2-9 July 2014, Tampa, Florida, pp. 332-33

  17. M. Balakrishnan, "Design of an Affordable and Flexible Braille Tutor", Blindness, Technology, and Multimodal Reading Conference, London, 27-28 June 2014

  18. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, "Series Expansion based Efficient Architectures for Double Precision Floating Point Division", CSSP, Springer Science, Appeared online May 15, 2014, DOI 10.1007/s00034-014-9811-8

  19. Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan, "Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array", (Poster paper) FCCM 2014, 11-13 May, Boston, pp 33

  20. Smruti R. Sarangi, Gayathri Ananthanarayanan, and M. Balakrishnan, "LightSim : A Leakage Aware Ultrafast Temperature Simulator", 19th ASP-DAC, 20-23 Jan 2014, Singapore, pp. 855-860

  21. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, "Accelerating Genome Assembly using Hard Embedded Blocks in FPGAs.", IEEE 27th International Conference on VLSI Design, 5-9 Jan 2014, Mumbai, pp. 306-311

  22. Dhruv Jain, Akhil Jain, Rohan Paul, Akhila Komarika and M. Balakrishnan, "A path-guided audio based indoor navigation system for persons with visual impairment" ASSETS 2013, 21-23 Oct Bellevue, Washington, pp. 33

  23. Anshul Singhal, Pranay Jain, Piyush Chanana, Dhruv Jain, Rohan Paul, M. Balakrishnan and P. V. M. Rao, "Application of Shape Memory Alloy (SMA) Based Actuation for Refreshable Display of Braille", ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications (MESA2013), Portland, Oregon, August 4-7, 2013, pp. ??

  24. Kolin Paul, M. Balakrishnan and Mansureh Shahraki Moghaddam, "Design and Implementation of high Performance Architectures with Partially Reconfigurable CGRAs", the 20th Reconfigurable Architectures Workshop, RAW 2013, Boston, May 2013

  25. Gayathri Ananthanarayanan, Geetika Malhotra, M. Balakrishnan, and Smruti R. Sarangi, "Amdahl's Law in the Era of Process Variation", Vol. 4, No. 4, 2013, International Journal of High Performance Systems Architecture (IJHPSA), pp. 218-230

  26. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier, "FAssem : FPGA based Acceleration of De Novo Genome Assembly" (short paper), FCCM 2013, April 2013, Seattle, USA

  27. Arun Parakh, M. Balakrishnan, Kolin Paul, "Performance Enhancemnt of Map-Reduce Framework on GPU", The 11th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2013, February 11-13, 2013, Innsbruck, Austria

  28. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, "Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs" 26th Proceedings of the International Conference on VLSI Design,, Pune, India, Jan 2013, pp. 92-97

  29. Arun Parakh, M. Balakrishnan, Kolin Paul, "Performance Estimation of GPUs with Cache", IPDPS Workshops 2012, Shanghai, China May 2012, pp. 2384-2393

  30. Sonali Chouhan, M. Balakrishnan, Ranjan Bose, "System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation", IEEE Trans. on CAD of Integrated Circuits and Systemsi, Vol. 31, No.4, 2012, pp. 586-596

  31. Rajeswari Devadoss, Kolin Paul, M. Balakrishnan, "Architecture and tools for programmable QCA", FPT 2011, Dec. 2011, Delhi, pp. 1-4

  32. P Panda, M Balakrishnan and A. Vishnoi, "Compressing Cache State for Post-Silicon Processor Debug", IEEE Transactions on Computers, Vol. 60, No. 4, April 2011, pp 484-497

  33. Rajeswari Devadoss, Kolin Paul, M. Balakrishnan, "p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata", JETC, Vol. 7, No. 3, 2011, Article No. 13

  34. R. Devadoss, K. Paul, M. Balakrishnan, "A Tiled Programmable Fabric using QCA", FPT 2010, Beijing, Dec. 2010, pp. 9-16

  35. Preeti Ranjan Panda, Anant Vishnoi and M. Balakrishnan, “Enhancing post-silicon processor debug with Incremental Cache state Dumping”, IEEE VLSI-SOC, Madrid, Spain, September 2010, pp. 55-60

  36. R. Devadoss, K. Paul, M. Balakrishnan, "Clocking-based Coplanar Wire Crossing Scheme for QCA", 23rd Proceedings of the International Conference on VLSI Design, Bengaluru, India, Jan. 2010, pp. 339-344

  37. R. Devadoss, K. Paul, M. Balakrishnan, “Coplanar QCA crossovers”, Electronics Letters, Volume 45,  Issue 24,  November 19 2009, pp.1234 – 1235

  38. Sonali Chouhan, Ranjan Bose, M. Balakrishnan, “Integrated Energy Analysis of Error Correcting Codes and Modulation for Energy Efficient Wireless Sensor Nodes”, IEEE Transactions on Wireless Communications, Volume 8,  Issue 10,  October 2009, pp. 5348 – 5355

  39. R. Devadoss, K. Paul, M. Balakrishnan, "Clocking-based Coplanar Wire Crossing Scheme for QCA", 1st International Workshop on Quantum-dot Cellular Automata, UBC, Vancouver, Canada, Aug. 2009.

  40. Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan, “Online Cache State Dumping for Processor Debug”. DAC 2009, pp. 358-363, Aug. 2009

  41. Sonali Chouhan, M. Balakrishnan, Ranjan Bose, “An Experimental Validation of System Level Design Space Exploration Methodology for Energy Efficient Sensor Nodes”, ISLPED 2009,  pp. 355-358, Aug. 2009

  42. Sonali Chouhan, Ranjan Bose, M. Balakrishnan, “A Framework for Energy Consumption Based Design Space Exploration for Wireless Sensor Nodes”, IEEE TCAD, Volume 28,  Issue 7,  July 2009, pp. 1017 – 1024

  43. Anant Vishnoi, Preeti Ranjan Panda and  M. Balakrishnan,  “Cache Aware Compression for Processor Debug Support”   Design Automation and Test in Europe (DATE), 20-24 April, Nice, France, pp. 208-213, April 2009

  44. Sahu, M. Balakrishnan and Preeti Ranjan Panda, “A Generic Platform for Estimation of Multi-threaded Program Performance on Heterogeneous Multiprocessor”, Design Automation and Test in Europe (DATE) 20-24 April, Nice, France, pp. 1018-1023, April 2009

  45. Kolin Paul,  M. Balakrishnan, Advait Jain, Pulkit Gambhir and Priyanka Jindal, “FPGA Accelerator for Protein Structure Prediction Algorithms” SPL 2009, Sao Carlos, Brazil, 1-3 April 2009, pp. 123-128

  46. Sonali Chouhan, M. Balakrishnan and Ranjan Bose, A Framework for Energy Consumption Based Design Space Exploration for Wireless Sensor Nodes, In International Symposium on Low Power Electronics and Design (ISLPED), Bangalore, India, pp. 329-334, Aug 2008.

  47. Anup Gangwar, M. Balakrishnan, Anshul Kumar and Preeti Ranjan Panda, ``Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures'', International Journal of Parallel Programming (IJPP), Springer, The Netherlands, vol 35, pp. 507-527, Dec 2007

  48. M Balakrishnan, Kolin Paul, Ankush Garg, Rohan Paul, Dheeraj Mehra, Vaibhav Singh, P.V.M. Rao, Vishwas Goel, Debraj Chatterjee, Dipendra Manocha,  “Cane Mounted Knee-above Obstacle Detection and Warning System for the visually impaired”,  3rd ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications (MESA 2007), Las Vegas, Nevada, USA, September 2007

  49. Ashutosh Pal and M. Balakrishnan, ``A Behavioral Synthesis Approach to Distributed Memory FPGA Architectures'', FPL 2007, Amsterdam, 27- 29 Aug. 2007, pp. 517-520

  50. Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul, Dipendra Manocha ,``Smart Cane for the Visually Impaired: Technological Solutions for Detecting Know above Obstacles and Accessing Public Buses'', Proc. of 11th International conference on Mobility and Transport for Elderly and Disabled Persons (TRANSED 2007), Montreal, Canada, June 2007

  51. Anup Gangwar, M. Balakrishnan and Anshul Kumar, ``Impact of Inter-cluster Mechanisms on ILP in Clustered VLIW Architectures'', ACM TODAES, Vol. 12, No. 1, Jan 2007, pp. 1-29. (Best Paper Award for ACM TODAES 2007)

  52. H. Dhand, Basant Dwivedi and M. Balakrishnan, ``New Approach to Architectural Synthesis: Incorporating QoS Constraint'', Proc. EMSOFT 2006, Seoul, Korea, Oct. 2006, pp.301-310.

  53. Basant K. Dwivedi, Arun Kejariwal, M. Balakrishnan and Anshul Kumar, ``Rapid Resource-Constrained Hardware Performance Estimation'', Proc. International Workshop on Rapid System Prototyping (RSP06), Chania, Crete, Greece, June 2006, pp 40-46.

  54. Akhilesh Chaudhary, Gaurav Gupta and M Balakrishnan, ``Factoring Large Numbers Using FPGAs'', Proc of VLSI Design and Test Symposium (VDAT 2005), Bangalore, India, August 2005

  55. Basant Kumar Dwivedi, Harsh Dhand, M.Balakrishnan and Anshul Kumar, ``RPNG: A Tool for Random Process Network Generation'', Proc of Asia and South Pacific International Conference in Embedded SoCs (ASPICES-2005), Bangalore, India, July 2005.

  56. Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda and Anshul Kumar,``Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures'', Proc. of Design Automation and Test in Europe (DATE05), Munich, Germany, March 2005, pp. 730-735

  57. Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, and Subhashis Banerjee, ``SMPS: An FPGA-based Prototyping Environment for Multiprocessor Embedded Systems'', IEEE/ACM Thirteenth International Symposium on Field Programmable Gate Arrays (FPGA-2005), Monterey, USA, February 2005

  58. Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar, ``Integrated On-chip Storage Evaluation in ASIP Synthesis'', Proc. 18th International Conference on VLSI Design (VLSI-2005), Kolkata, India, January 2005, pp 274-279.

  59. Gaurav Arora, Abhishek Sharma, M. Balakrishnan and D. Nagchoudhuri, ``ADOPT - An Approach to Activity Based Delay Optimization'', Proc. 18th International Conference on VLSI Design (VLSI-2005), Kolkata, India, January 2005, pp. 411-416.

  60. Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar, ``Efficient Technique for Exploring Register File SIze in ASIP Design'', IEEE TCAD of VLSI, vol. 23, No. 12, pp. 1693-1699, Dec. 2004.

  61. Basant Kumar Dwivedi, Anshul Kumar and M.Balakrishnan, ``Automatic Synthesis of System on Chip Multiprocessor Architectures for Process Networks '', ISSS 2004, Sep. 8-10, 2004, Stockholm, Sweden, pp. 60-65.

  62. Basant Kumar Dwivedi, Anshul Kumar and M.Balakrishnan, ``Synthesis of  Application Specific Multiprocessor Architectures for Process Networks'',  Proc. 17th International Conference on VLSI Design, January 2004, Mumbai, India, pp. 780-787.

  63. Anup Gangwar, M. Balakrishnan and Anshul Kumar, ``Impact of Inter-cluster Communication Mechanisms on ILP in Clustered VLIW Architectures'', Proc. of the Workshop on Application Specific Processors (WASP-2, held in conjunction with MICRO-36), San Diego, USA, Dec. 2003, pp. 56-63.

  64. Manoj Kumar Jain, M.Balakrishnan and Anshul Kumar, ``Exploring Storage Organization in ASIP Synthesis'', Euromicro Symposium on Digital System Design (Euro-DSD 2003), September 2003, Belek Near Antalya, Turkey, pp. 120-127.

  65. Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant K. Dwivedi, M. Balakrishnan and Anshul Kumar "SoC Synthesis with Automatic Interface Generation", Proc. of 16th International Conference on VLSI Design (VLSI-2003), January 2003, New Delhi, India, pp. 585-590.

  66. Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar, ``An Efficient Technique for Exploring Register File Size in ASIP Synthesis", Proc. of CASES 2002, Grenoble, France, Oct. 2002, pp. 252-261.

  67. C.P. Joshi, Anshul Kumar and M. Balakrishnan, "A New Performance Evaluation Approach for System Level Design Space Exploration", Proc. of ISSS02, October 2002, Kyoto, Japan, pp. 180-185.

  68. Bhuvan Middha, Varun Raj, Anup Gangwarm Anshul Kumar, M. Balakrishnan and Paolo Ienne, "A TRIMARAN Based Framework for Exploring the Design Space of VLIW ASIPS with Coarse Grain Functional Units", Proc. of ISSS02, October 2002, Kyoto, Japan, pp. 2-7.

  69. Stefan Steinke, Nils Grunwald, Lars Wehmeyer, Rajeshwari Banakar, M. Balakrishnan and Peter Marwedel, "Dynamic copying of Instructions into Onchip Memory for Energy Reduction", Proc. of ISSS02, October 2002, Kyoto, Japan, pp. 213-218.

  70. Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan and Peter Marwedel, "Scratchpad Memory: A Design Alternative for Cache On-chip Memory in Embedded Systems", Proc. of CODES 2002, Estes Park, Colorado, May 2002, pp. 73-78. (2nd most cited paper published in CODES/ISSS in 10 years; listed by Frank Vahid and Tony Givargis,  “Highly Cited Ideas in System Codesign and Synthesis”, CODES+ISSS’08, October 19–24, 2008, Atlanta, Georgia, USA)

  71. K.N. Murali Mohan, Rohini Krishnan, Anshul Kumar and M. Balakrishnan, " A New Divide and Conquer Method for Achieving High-speed Division in Hardware", Proc. of VLSI Design/ASPDAC 2002, Bangalore, India, Jan. 2002, pp. 535-540.

  72. Vishal P. Bhatt, M. Balakrishnan and Anshul Kumar, `` Exploring the Number of Register Windows in ASIP Synthesis", Proc. of VLSI Design/ASPDAC 2002, Bangalore, India, Jan. 2002, pp. 233-238.

  73. L. Wehmeyer, Manoj Jain, Stefan Steinke, Peter Marwedel and M. Balakrishnan, "Analysis of the Influence of Register File Size on Energy Consumption, Code Size and Execution Time" IEEE TCAD, vol. 20, no. 11, Nov. 2001, pp. 1329-1337.

  74. Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel and M. Balakrishnan, "Evaluating Register File Size in ASIP Design", Proc. of CODES 2001, Copenhagen, April 2001, pp. 109-114.

  75. Basant K. Dwivedi, Jan Hoogerbrugge, Paul Stravers and M. Balakrishnan, "Exploring Design Space of Parallel Realizations: MPEG-2 Decoder Case Study", Proc. of CODES 2001, Copenhagen, April 2001, pp. 92-97.

  76. Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar, ``ASIP Design Methodologies: Survey and Issues", Proc. of the Intl. Conf. on VLSI Design, Bangalore, India, Jan. 2001, pp. 76-81.

  77. Anupam Rastogi, M. Balakrishnan and Anshul Kumar, ``Integrating Communication Cost Estimation in Embedded Systems Design: A PCI Case Study", Proc. of the Intl. Conf. on VLSI Design, Bangalore, India, Jan. 2001, pp. 23-28.

  78. Vivek Haldar, Gokul Varadhan, Abhishek Saxena, M. Balakrishnan and Subhashis Banerjee, ``Design of Embedded Systems for Real-Time Vision", Proc. Indian Conf. on Computer Vision, Graphics and Image Processing, (ICVGIP'2000), Bangalore, India, Dec. 2000.

  79. M. Balakrishnan and Heman Khanna, ``Allocation of FIFO Structures in RTL Data Paths", ACM TODAES, July 2000, pp. 294-310.

  80. Akshaye Sama, M. Balakrishnan and J.F.M. Theeuwen, ``Speeding up Power Estimation of Embedded Software", Proc. of ISLPED, 23-24th July 2000, Italy, pp. 191-196.

  81. Arvind Rajawat, M. Balakrishnan and Anshul Kumar,``Interface Synthesis : Issues and Approaches", Proc. of 13th Intl. Conf. on VLSI Design, IEEE CS Press, Calcutta, India, Jan. 2000, pp.92-97

  82. T. Vinod Kumar, P. Sharma, M. Balakrishnan and S. Malik, ``Processor Evaluation in an Embedded Systems Design Environment", Proc. of 13th Intl. Conf. on VLSI Design, IEEE CS Press, Calcutta, India, Jan. 2000, pp.98-103

  83. Aviral Srivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar and M. Balakrishnan,``Optimal Hardware/Software Partitioning for Concurrent Specification using Dynamic Programming", Proc. of 13th Intl. Conf. on VLSI Design, IEEE CS Press, Calcutta, India, Jan. 2000, pp.110-113

  84. Ajoy Chakravarthy and M. Balakrishnan,``Simulation and Modeling of a Multi-cast ATM Switch", Proc. of the 12th CSI/IEEE Intl. Conf. on VLSI Design, Goa, India, Jan. 1999, pp.242-247

  85. Rashmi Goswami, V. Srinivasan and M. Balakrishnan, ``MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign", Proc. of 12th CSI/IEEE Intl. Conf. on VLSI Design, Goa, India, Jan. 1999, pp. 128-131

  86. A.R. Naseer, M. Balakrishnan and Anshul Kumar, ``Direct Mapping of RTL Structures onto LUT based FPGAs'', IEEE TCAD of Integrated Circuits and Systems, Vol 17, No. 7, July 1998, pp. 624-631

  87. S.K. Lodha, Shashank Gupta, M. Balakrishnan and S. Banerjee,``Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign'',Proc. of  11th CSI/IEEE Intl. Conf. on VLSI Design, Chennai, India, Jan. 1998, pp. 97-102

  88. Sitanshu Jain,  M. Balakrishnan, Anshul Kumar and Shashi Kumar,``Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library'',Proc. of  11th CSI/IEEE Intl. Conf. on VLSI Design, Chennai, India, Jan. 1998, pp. 400-405

  89. A.R. Naseer, M. Balakrishnan and Anshul Kumar, ``Optimal Clock Period for Synthesized Data Paths'', Proc. of  10th Intl. Conf. on VLSI Design, Hyderabad, India, Jan. 1997, pp. 134-139.

  90. Gaurav Agarwal, Nitin Thapar, Kamal Agarwal, M. Balakrishnan and Shashi Kumar, ``A Novel Reconfigurable Co-processor Architecture'', Proc. of  10th Intl. Conf. on VLSI Design, Hyderabad, India, Jan. 1997, pp. 370-375

  91. Heman Khanna and M. Balakrishnan, ``Allocation of FIFO Structures in RTL Data Paths'', Proc. of  10th Intl. Conf. on VLSI Design, Hyderabad, India, Jan. 1997, pp. 130-133.

  92. A.R. Naseer, M. Balakrishnan and Anshul Kumar, ``A Novel Approach to Direct Realization of RTL Structures using FPGAs'', Proc. of Intl. Workshop on Logic and High Level Synthesis, Grenoble, France, December 1996

  93. Alok Mittal,Aditya Vailaya, S, Banerjee and M. Balakrishnan, "Real Time Vision System for Collision Detection" CSI Journal of Computer Science and Informatics, March 1995, pp. 13-29. (Best Paper Award of CSI Journal of Computer Science and Informatics 1995)

  94. Alok Kumar, Anshul Kumar and M. Balakrishnan," Heuristic Search based Approach to Scheduling, Allocation and Binding in Data Path Synthesis", Proc. of  8th CSI/IEEE Intl. Conf. on VLSI Design, Delhi, India, Jan. 1995, pp. 75-80.

  95. Varshneya, B.B. Madan and M. Balakrishnan," "Memory Coupled Scalable Multiprocessors" Proc. of the 1st Workshop on Parallel Processing, Bangalore, India, Dec. 1994, pp. 424-429.

  96. A.R. Naseer, M. Balakrishnan and Anshul Kumar, "An Efficient Technique for Mapping RTL Structures onto FPGAs", Proc. FPL '94, Prague, Czech Republic, Sep. 1994, LNCS vol-849, pp. 89-110.

  97. Varshneya, B.B. Madan and M. Balakrishnan," Concurrent Search and Insertion in K-Dimensional Height Balanced Trees", Proc. of Intl. Parallel Processing Symposium, Cancun, Mexico, May 1994, pp.883-887.

  98. A.R.Naseer, M.Balakrishnan and Anshul Kumar, "A Technique for Synthesizing Data Part Using FPGAs ", Proc. of 2nd IEEE/ACM Intl. Symp. on FPGAs, Berkeley, California, Feb. 1994.

  99. A.R.Naseer, M.Balakrishnan and Anshul Kumar, "FAST : FPGA Targeted RTL Structure Synthesis Technique", Proc. of 7th CSI/IEEE Intl. Conf. on VLSI Design, Calcutta, India, Jan. 1994, pp.21-24.

  100. M.V. Rao, M. Balakrishnan and Anshul Kumar, "DESSERT: Design Space Exploration of RT Level Components", Proc. of 6th CSI/IEEE Intl. Conf. on VLSI Design, Bombay, India, Jan. 1993, pp. 299-304.

  101. P.P. Nedungadi, M. Balakrishnan and Anshul Kumar, "Data Path Synthesis with Global Time Constraint",(Poster Paper) Proc. of 5th CSI/IEEE Intl. Conf. on VLSI Design,  Bangalore, India, Jan. 1992, pp.322-323.

  102. Alok Kumar, Anshul Kumar and M. Balakrishnan, " A Novel Integrated Scheduling and Allocation Algorithm for Data Path Synthesis", Proc. of VLSI Design '91, IEEE Computer Society Press, New Delhi, Jan. 1991, pp.212-218.

  103. B.L. Priyadarshan, M. Balakrishnan, Anshul Kumar and G.S. Vishweswaran, "SYMCAD : Synthesis of Microprogrammed Control for Automated VLSI Design", Proc. of Intl. Workshop of Microprogramming (MICRO-23), Orlando, Florida, Nov. 1990, pp. 176-182.

  104. M.Balakrishnan and Anshul Kumar, "A Comparative Study of Techniques for Synthesis of Optimal Structures from Behavioral Descriptions", Proc. Of VLSI Design, Bangalore, India, Jan. 1990. (Reprinted in MicroArch, IEEE Technical Committee on Computer Architecture, Vol. 5, No. 1, April 1990, pp. 2-7.

  105. M.Balakrishnan and P.Marwedel, "Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration", Proc. of 26th Design Automation Conference, '89, Las Vegas, Nevada, USA, June 1989 pp.68-74.

  106. M.Balakrishnan, A.K.Majumdar, D.K.Banerji and J.G.Linders, "Synthesis of Decentralized Controllers from High Level Description", Euromicro Journal of Microprocessing and Microprogramming, Vol. 22, No. 3, May 1988, pp 217-229.

  107. M.Balakrishnan, A.K.Majumdar, D.K.Banerji, J.G.Linders and J.C.Majithia, "Allocation of Multiport Memories in Data Path Synthesis", IEEE TCAD of Integrated Circuits and Systems, vol 7, April 1988, pp 536-540.

  108. M.Balakrishnan, A.K.Majumdar, D.K.Banerji, J.G.Linders and J.C.Majithia, "A Semantic Approach to Modular Synthesis of VLSI Systems", Information Processing Letters, Vol 27, No. 1, Feb. 1988, pp 1-7.

  109. M.Balakrishnan, B.B.Madan and P.C.P.Bhatt, "An Efficient Retargetable Micro-code Generating System", Euromicro Journal of Microprocessing and Microprogramming, Vol. 19, No. 4, Oct. 1987, pp 305-318.

  110. M.Balakrishnan, P.C.P.Bhatt and B.B.Madan, "A Survey of Microprogramming Languages", Euromicro Journal of Microprocessing and Microprogramming, Vol. 17, No. 1, Jan. 1986, pp 19-27.