Home
About me
Research
Resume
Links
Photos
Teaching Assistantship
 
Areas of Intrest

Multicore Processor Architectures

Low Power Design
Current Projects

1. Multicore Interconnect Modeling

  • This project aims to provide a framework for fast and accurate performance and power analysis of Network-On-Chip architectures. Project details are available here

2. Hardware Acceleration of Trace-driven NoC Simulations

Publications

Design of Reconfigurable Datapath for Multi-Standard Viterbi and Turbo Decoder - G.Krishnaiah, N.Engin and S.Sawitzki, Technical Note PR-TN 2006/00381, Philips Research Europe.

Scalable reconfigurable channel decoder architecture for future wireless handsets. - G.Krishnaiah, N.Engin and S.Sawitzki, DATE 2007, Nice, France.

Unified Modeling Abstraction for Fast Simulation and Emulation - Gummidipudi Krishnaiah, P.R.Panda, Ashok Janannathan, Sreenivas Subramoney and Anshul Kumar, in WARP 2008 Beijing, China.

Rank Based Dynamic Voltage and Frequency Scaling for Tiled Graphics Processors - B. V. N. Silpa, Gummidipudi Krishnaiah, and Preeti Ranjan Panda, in CODES+ISSS 2010, Scottsdale, USA (Best Paper Candidate ).

FastFwd: An Efficient Hardware Acceleration Technique for Trace-driven Network-on-Chip Simulation - Gummidipudi Krishnaiah, B.V.N.Silpa, Preeti Ranjan Panda and Anshul Kumar, in CODES+ISSS 2010, Scottsdale, USA.

Power-efficient System Design - Preeti Ranjan Panda, Aviral Shrivastava, B.V.N. Silpa, Gummidipudi Krishnaiah, by Springer Publications, 2010, USA.

Exploiting Temporal Decoupling to Accelerate Trace-driven NoC Emulation - Gummidipudi Krishnaiah, B.V.N.Silpa, Preeti Ranjan Panda and Anshul Kumar, in CODES+ISSS 2011, Taipei, Taiwan.