Tejas is a cycle accurate
architectural simulator that is developed by our research group
(Srishti) at IIT Delhi. The simulator has been written entirely in
Java, and is shown to be the fastest open-source (Apache v2 license)
cycle accurate simulator worldwide (800+ users). I am one of the major
contributors (57,000+ lines of code) to this project. The primary
contributions include:
- Translation engine : Implemented the translation engine of Tejas. The
translation engine converts instructions from x86 to VISA. VISA is the ISA
of Tejas; it abstracts the idiosyncrasies of a complex ISA like x86 and is
sufficient for timing simulation.
- Communication Channel : Designed and implemented the plug and
play communication channel of Tejas. It provides seamless support for
emulators such as Pin, Qemu, and GPGPU over different communication
channels such as shared memory, network, and files.
- Memory System : Designed and implemented the memory system (cache,
directory, coherence, interface with chip interconnect) of Tejas along with a
fellow Ph.D. student Rajshekar Kalayappan.
Qemu is an open source emulator that can run unmodified operating systems.
We developed a patch to Qemu called QemuTrace that provides full system
execution traces. These traces are important for studying the execution of system
intensive workloads in virtualized as well as native environments. My primary
contributions include:
- Instrumentation : Instrumented Qemu to generate full system execution
traces that include an assembly text of instructions executed, load/store
addresses, branch outcomes, system calls, interrupts and privilege level
switches in x86.
- Non-intrusive recording : Ported a research prototype of Qemu
record/replay framework to QemuTrace.