Neeraj Goel has received B. Tech. degree from NIT Kurukshetra in Electronics and Communication in 2002; M.Tech. from IIT Delhi in VLSI Design Tools & Technology in 2004; PhD from Computer Science and Engg. Department, IIT Delhi in 2012. His final project for M.Tech. was done in Philips Research, Eindhovan, The Netherlands; and was about Hardware Software co-design of an Algorithm. His PhD dissertation title was Scalable and Low Power Register File Design for VLIW Processors He is currently working as Senior R & D Engineer for Synopsys. His research interest includes embedded processors (like VLIWs) and their tools and compilers; behavioral synthesis, system level design, FPGAs and reconfigurable computing. For his PhD thesis he worked for reducing the complexity of multi-ported register files in high issue VLIW processor. He has suggested a reduced port register file architecture which reduces power/energy for a given issue width processor and lead to a scalable register file design.
Detailed Resume (slightly out of date, mail me for current version)