| News Archive |
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2020 |
| [Feb 2020] Survey paper A survey of cache simulators by H. Brais et al. published in ACM Computing Surveys, Feb 2020 |
| [Jan 2020] P. R. Panda is appointed Editor-in-Chief of IEEE Embedded Systems Letters (ESL) journal |
2019 |
| [Nov 2019] Neetu Jindal is conferred the PhD degree at IITD's 50th Convocation ceremony. She was part of the research collaboration with Freescale/NXP and SRC. Now at Intel. |
| [Oct 2019] Research paper PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor by L. Siddhu and P. R. Panda presented at CODES+ISSS'19 , New York |
| [Oct 2019] Research paper Alleria: An Advanced Memory Access Profiling Framework by H. Brais and P. R. Panda presented at CODES+ISSS'19 , New York |
| [Oct 2019] Research paper REAL: REquest Arbitration in Last Level Caches by S. Tiwari, S. Tuli, I. Ahmad, A. Agarwal, P. R. Panda, and S. Subramoney, to appear in ACM TECS |
| [Aug 2019] New research project Algorithms and Architectures for Machine Learning and Computing on the Edge sponsored by Cadence Design Systems initiated. |
| [Aug 2019] Book chapter Manycore processor architectures by P. Chakraborty, B. N. Swamy, and P. R. Panda published in Many-Core Computing: Hardware and Software, eds. B. M. Al-Hashimi and G. V. Merrett, IET |
| [Jul 2019] P. R. Panda delivered the keynote address at VDAT'19, Indore |
| [Jun 2019] Research paper DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring by Neetu Jindal, Sandeep Chandran, et al. presented at DAC 2019 |
| [Mar 2019] Research paper "FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories" by Lokesh Siddhu and P. R. Panda presented at DATE'19, Florence. |
| [Feb 2019] Research paper Enhancing Network-on-Chip Performance by Reusing Trace Buffers by Neetu Jindal,Shubhani Gupta, Divya Praneetha et al. accepted for publication in IEEE Transactions on CAD. |
| [Jan 2019] Rahul Jain wins the Best PhD Thesis Award at the 32nd Intl. Conf. on VLSI Design and 18th Intl. Conf. on Embedded Systems for his thesis titled Machine Learned Machines: Reinforcement Learning Exploration for Architecture Co-optimization. The research was supported by Intel and DST/SERB's PM Fellowship program. |
| [Jan 2019] Ayushi Agrawal (with team-mates Anupam Sobti and Saurabh Tewari) wins the first prize in the Cadence Tensilica Hackathon at VLSID 2019. |
| [Jan 2019] P. R. Panda is the general co-chair of the 32nd Intl. Conf. on VLSI Design and 18th Intl. Conf. on Embedded Systems |
2018 |
| [Nov 2018] Sandeep Chandran is awarded the PhD degree at the 49th Convocation. Wins the FITT Award (incl. cash prize of Rs. 60,000) for the Best Industry Relevant PhD Project in IIT Delhi. Freescale/NXP Semiconductor and Semiconductor Research Consortium were collaborators. |
| [Nov 2018] Research paper "FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories" by Lokesh Siddhu and P. R. Panda accepted for presentation at DATE'19, Florence. |
| [Sep 2018] P. R. Panda is Head, Amar Nath and Shashi Khosla School of Information Technology, IIT Delhi |
| [Jul 2018] Isaar Ahmed, Aritra Bagchi, and Ayushi Agarwal join our research group. Welcome! |
| [Apr 2018] Research paper "Reusing Trace Buffers as Victim Caches" by N. Jindal, P. R. Panda, and S. R. Sarangi accepted for publication in IEEE Transactions on VLSI Systems. |
| [Apr 2018] Lecture video series for the online course "Synthesis of Digital Systems" available on Youtube. |
| [Jan 2018] Book chapter: P. R. Panda, "Memory Architectures" published in S. Ha and J. Teich, "Handbook of Hardware/Software Codesign", Springer, 2017. |
| [Jan 2018] P. R. Panda is an Associate Editor of IEEE Transactions on CAD. |
| [Jan 2018] P. R. Panda is an Associate Editor of IEEE Transactions on Multi-Scale Computing Systems. |
2017 |
| [Oct 2017] Rahul Jain receives his PhD degree. His research was part of an Intel collaboration. Now at Reniac. |
| [Aug 2017] Research paper "Cooperative Multi-Agent Reinforcement Learning based Co-optimization of Cores, Caches, and On-chip Network" by R. Jain, P. R. Panda, and S. Subramoney accepted for publication in ACM Transactions on Architecture and Code Optimization. |
| [Jun 2017] New Research Project on Smartphone Energy Efficiency sponsored by Samsung initiated. |
| [May 2017] New Research Project on Memory Hierarchy in Multiprocessor Systems-on-Chip sponsored by Semiconductor Research Corporation (SRC) initiated. |
| [Mar 2017] Research paper "A Coordinated Multi-Agent Reinforcement Learning Approach to Multi-Level Cache Co-partitioning" by Rahul Jain, P. R. Panda, and S. Subramoney, presented at DATE'17, Lausanne. |
| [Mar 2017] Research paper "Reusing Trace Buffers to Enhance Cache Performance" by Neetu Jindal, P. R. Panda, and S. R. Sarangi, presented at DATE'17, Lausanne. |
| [Feb 2017] P. R. Panda delivered inaugural talk "Embedded Systems-on-Chip: Research at the Forefront of VLSI Systems" and seminars on Hardware Synthesis at Faculty Development Programme in MNIT Jaipur. |
| [Jan 2017] Research paper "Managing Trace Summaries to Minimize Stalls During Post-silicon Validation" by S. Chandran, P. R. Panda S. R. Sarangi, A. Bhattacharya, D. Chauhan, and S. Kumar, to appear in IEEE Transactions on VLSI Systems. |
2016 |
| [Nov 2016] Research paper "A Coordinated Multi-Agent Reinforcement Learning Approach to Multi-Level Cache Co-partitioning" by Rahul Jain, P. R. Panda, and S. Subramoney, accepted for presentation at DATE'17, Lausanne. |
| [Nov 2016] Research paper "Reusing Trace Buffers to Enhance Cache Performance" by Neetu Jindal, P. R. Panda, and S. R. Sarangi, accepted for presentation at DATE'17, Lausanne. |
| [Oct 2016] Prof. Sri Parameswaran from Univ. of New South Wales visits the dept. and delivers a seminar on "QUADSEAL: A Hardware Countermeasure against Side channel Attacks on AES". |
| [May 2016] Research paper "Partitioning and Data Mapping in Reconfigurable Cache and Scratch Pad Memory based Architectures" by P. Chakraborty, P. R. Panda, and S.Sen accepted for publication in ACM Transactions on Design Automation of Electronic Systems. |
| [Mar 2016] Research paper "Machine Learned Machines: Adaptive Co-optimization of Caches, Cores, and On-chip Network" by R. Jain, P. R. Panda, and S. Subramoney, receives Best Interactive Presentation nomination at DATE'16, Dresden. |
| [Jan 2016] Research paper "Extending Trace History Through Tapered Summaries in Post-silicon Validation" by S. Chandran, P. R. Panda, S. R. Sarangi, D. Chauhan, and S. Kumar, receives Best Paper nomination at ASPDAC'16, Macau. |
| [Jan 2016] Prof. Chita Das from Penn State Univ. visits the dept. and delivers a seminar on "Architecting Next-Generation Mobile Platforms". |
| [Jan 2016] P. R. Panda was a member of the panel discussing "The Changing Indian Landscape, and Implications to University-Industry Collaboration" at Semiconductor Research Consortium India Design Review 2016, Bangalore. |
| [Jan 2016] Sandeep presented the research paper "A Generic Implementation of Barriers using Optical Interconnects" by S. Chandran, E. Peter, P. R. Panda, S. R. Sarangi, at VLSI Design'16, Kolkata. |
| [Jan 2016] P. R. Panda is an Associate Editor of IEEE Embedded Systems Letters starting 2016. |
2015 |
| [Dec 2015] Research paper "Area-Aware Cache Update Trackers for Postsilicon Validation" by S. Chandran, S. R. Sarangi, and P. R. Panda, to appear in IEEE Transactions on VLSI Systems. |
| [Oct 2015] Research paper "Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures" by I. Filippopoulos, N. Sharma, P. G. Kjeldsberg, F. Catthoor, P. R. Panda to appear in ACM Transactions on Embedded Computing Systems. |
| [Oct 2015] Namita Sharma and Prasenjit Chakraborty are conferred the PhD degree. |
| [Oct 2015] Namita Sharma presents the research paper "Energy Efficient FFT Implementation through Stage Skipping and Merging" by N. Sharma, P. R. Panda, and F. Catthoor in CODES+ISSS'15, Amsterdam. |
