List of Current Projects


Hardware Projects: Power/Temperature modeling, post-silicon debugging, devices for optical interconnects.

Computer Architecture Projects: Efficient on-chip networks (electrical and optical), reliability enhancing techniques, hardware support for operating systems.
Software Projects: Operating systems for parallel multicore processors, massively parallel architectural simulation, software for the internet-of-things, concurrent data structures for multicore processors, ethical hacking using virtual machines.


Power and Temperature Modeling of Processors

At the lowest level, we focus on process variation, and temperature modeling. In my Ph.D I have worked on process variation and released the first widely available toolkit for modeling process variation in multicore processors. Our research in IIT Delhi is focused primarily on temperature modeling. We have released the LightSim toolkit that uses a fast Green's function based approach for estimating temperature in both 2D and 3D chips. We use this framework to design power and temperature control mechanisms in large manycore chips. We are extending this framework to model server noise also.

Representative Publications: [Sarangi et al., ASPDAC '14]


Reliability and Processor Debugging

In spite of advances in circuit design, it is not always possible to hide faults. It is thus necessary to debug processors even after release. Several of our students are currently working on post-silicon debugging. We work on creating new hardware structures to efficiently collect traces of program execution and analyze them offline. The aim is to also create customizable units that detect a very wide variety of hardware bugs. Additionally, we also look at tolerating both transient and permanent faults in hardware. One of my Ph.D students is working on checker architectures. We have proposed a new technique called FluidCheck (submitted to ACM Transactions on Architecture, TACO) to verify the execution of a set of applications running on a large manycore processor. This framework has been recently extended to also create an architectural mechanism for collecting detailed traces in an SoC with third party accelerators. We can use such mechanisms to detect malicious behavior in hardware..

Representative Publications: [Kalayappan et al. ISVLSI '15, ACM Computing Surveys '13, Chandran et al., Date '13]


On Chip Networks

Some of my Master's and Ph.D students are also looking at on-chip networks, particularly optical networks. We have proposed a novel on-chip optical network that dissipates 4X less power than state of the art techniques, and we have used this to design novel protocols for implementing barriers, and non-uniform caches. We also have done some work in co-designing networks and L2 cache protocols.

Representative Publications: [Peter et al. Silicon Photonics '15, Peter et al. HiPC '14, Arora et al. IEEE Trans. on Parallel and Dist. Systems '15]


Hardware Support for Operating Systems, and Efficient Operating System Design for Parallel Processors

Another thrust area for us is hardware support for operating systems. We have proposed a variety of techniques for reducing the interference caused by operating systems in the execution of performance sensitive programs. Our proposals include novel voltage-frequency modulation techniques to reduce OS jitter and operating system caches for storing the memory footprint of the OS. We will be collaborating with Netapp, Bangalore, for a project that looks at designing a futuristic OS for storage and analytics based workloads.

Representative Publications: [Chandran et al. IEEE Trans. on Parallel and Dist. Systems '14, Bhalla et al. HiPC '14]


Novel Data Structures for Multicore Processors

At the level of software, we work in designing novel data structures for multicore systems. One of my students, who recently submitted her Ph.D thesis, worked on non-blocking algorithms for slot schedulers. We were able to design parallel non-blocking schedulers that were 10 times faster than existing alternatives. They are ideally suited for novel workloads such as micro-blogging and algorithmic trading. We have also worked on wait-free stacks, and novel data structures for garbage collection.

Representative Publications: [Aggarwal et al. IEEE Trans. on Parallel and Dist. Systems '15, IPDPS '13, HiPC '14]


Multicore Architecture Simulation

We have also worked heavily on multicore architecture simulation in the past We have released the first publicly available Java based multicore simulator called Tejas. It supports almost all the features supported by other contemporary simulators. It is faster (by roughly 1.5-2X) and is more accurate that competing simulators. As a part of the Tejas simulator family, we have released other open source software: emuArm (GUI based ARM emulator), Tejas-Java (Java bytecode simulator), GPU-Tejas, and ParTejas (parallel Tejas). These programs have been downloaded 500+ times by users worldwide (link). These simulators are being used to teach courses and conduct research in IIT Delhi, as well as many many other institutes worldwide.
Representative Publications: [Malhotra et al, ISPASS 2014, Sarangi et al. PATMOS 2015]