Shibashis Guha Research Scholar, Department of Computer Science and Engineering, Indian Institute of Technology, Delhi. Email : shibashis AT cse DOT iitd DOT ac DOT in Research Interest: Timed Automata, Timed Process Algebra Advisor: Prof. S. Arun-Kumar.

Work-related:

• Courses at IIT Delhi: Data Structures and Algorithms, Foundations of Automatic Verification, Compiler Design, Operations Research
• Teaching Assistantship: Logic for Computer Science(CSL303), Programming Languages(CSL302), Discrete Mathematics(CSL105)

Research Work:

• "On Decidability of Prebisimulation for Timed Automata", S. Arun-Kumar, Shibashis Guha and Chinmay Narayan. Accepted in CAV 2012
• An extended version of the CAV 2012 paper, S. Arun-Kumar, Shibashis Guha and Chinmay Narayan. Technical Report
• "Deciding Timed Bisimulation for Timed Automata Using Zone Valuation Graph", S. Arun-Kumar, Shibashis Guha and Chinmay Narayan. Technical Report
• "LogicFence: A Framework for Enforcing Global Integrity Constraints at Runtime", Shibashis Guha, Srinath Srinivasa, Saikat Mukherjee and Ranajoy Malakar, in Proceedings of the 10th International Database Engineering and Application Symposium (IDEAS 2006), New Delhi, India
• "Enforcement of Global Integrity Constraints in a Multi-Process System at Runtime", Shibashis Guha, M Tech thesis at International Institute of Information Technology, Bangalore

Personal links:

• Blogs


• goodreads


• Udyam Prayas

Resources

• MACS (Modelling and Analysis of Complex Systems) at IIT Delhi (for internal users only).