3rd Floor, Bharti Building
Department of Computer Science and Engineering
Indian Institute of Technology Delhi
New Delhi 110 016, INDIA.
Email: shibashis @ cse. iitd. ac. in
I am a PhD student working on behavioural equivalences and preorders over timed automata. I am exploring the decidability of various behavioural relations that are relevant for timed automata. I am also interested in constructing timed automata with reduced state space while preserving some equivalence relation. I am advised by Prof. S. Arun-Kumar and my research is supported by Microsoft Research India PhD Fellowship.
- Timed automata
- Bisimulation, behavioural equivalences
- Automata, logic, games for controller synthesis
News and Updates
I am currently visiting the Centre for Formal Design and Verification of Software at IIT Bombay where I am working with Krishna. S and Ashutosh Trivedi on games over timed automata. I am working on robust semantics of timed automata and mean payoff games for timed automata.
- A short course on Timed Automata in May 2014 as part of the course Foundations of Automatic Verification: The participants were introduced to timed automata, region equivalence and region graphs, relation between region equivalence and time abstracted bisimulation, PSPACE completeness of reachability in TA, NL completeness for reachability for one-clock TA, undecidability of universality problem for timed automata, timed and time abstracted bisimulation.
- Bisimulations and Prebisimulations for Timed Automata, ACM IRISS, , February 2015 at Goa, India.
- Reducing Clocks in Timed Automata while Preserving Bisimulation, CONCUR September 2014 at Rome, Italy.
- Timed bisimilarity through model checking and Related problems, Formal Methods Update Meeting, July 2014 at IIT Kharagpur, India
- A Unifying Approach to Decide Relations for Timed Automata and their Game Characterization, EXPRESS/SOS , August 2013 at Buenos Aires, Argentina
- An Introduction to Timed Automata, CFDVS, IIT Bombay , December 2012 at Mumbai, India
- On Decidability of Prebisimulation for Timed Automata, CAV , July 2012 at Berkeley, California, USA
- Game Characterizations of Timed Bisimulations, Formal Methods Update Meeting , July 2012 at Chennai Mathematical Institute, India
- "Revisiting Robustness in Priced Timed Games", with Lakshmi Manasa , Krishna S and Ashutosh Trivedi , (Submitted)
- "Reducing Clocks in Timed Automata while Preserving Bisimulation",
with Chinmay Narayan and S. Arun-Kumar ,
in Proceedings of CONCUR 2014, Rome, Italy
- "A Unifying Approach to Decide Relations for Timed Automata and their Game Characterization",
with Krishna S, Chinmay Narayan and S. Arun-Kumar ,
in Proceedings of EXPRESS/SOS 2013, Buenos Aires, Argentina
- "On Decidability of Prebisimulation for Timed Automata",
with Chinmay Narayan and S. Arun-Kumar,
in Proceedings of CAV 2012, Berkeley, California, USA
- "LogicFence: A Framework for Enforcing Global Integrity Constraints at Runtime",
with Srinath Srinivasa, Saikat Mukherjee and Ranajoy Malakar,
in Proceedings of the 10th International Database Engineering and Application Symposium (IDEAS 2006), New Delhi, India
- "Enforcement of Global Integrity Constraints in a Multi-Process System at Runtime",
M Tech thesis at International Institute of Information Technology, Bangalore
- LogicFence: A Java based framework that enforces global integrity constraints across multiple applications at runtime.
The tool can be downloaded from here.
- ReLTS: This tool provides a game based approach for checking a set of generalized
form of behavioural relations that includes bisimulation, simulation preorder
and equivalences over labelled transition systems and time abstracted relations
for timed automata
This tool is currently under development. The latest version is available at this link.
Awards and Honors
- Microsoft Research India PhD Fellowship 2012
- Outstanding TA Award for the courses Data Structures, (Spring semester, 2014) and Logic in Computer Science (Autumn Semester, 2012)
- Microsoft Research India travel grant in 2012
- ACM India-IARCS travel grant in 2012 and 2014
- Honeywell Scholarship for outstanding academic excellence during M Tech
- Topper in Bachelor of Engineering in Information Technology from University of Calcutta
- Placed within top 5 in C-DAC D level computer science prociency examination conducted throughout India
- Organized Formal Methods Update Meeting 2013 (July 27-28 at IIT Delhi).
- External reviewer for FORTE 2014, FORMATS 2014, FORTE 2015, VMCAI 2015