Sanjana Singh

Research Scholar
Department of Computer Science & Engineering
IIT Delhi

Sanjana Sanjana

Advisor: Subodh Sharma

Reaseach Area: Program Analysis of Relaxed Memory Concurrency

Member: Vertecs Group

Find Me: Verification Lab
3rd floor, Bharti Building (Block IIA)
IIT Delhi

About Me
I'm a research scholar in the Department of Computer Science & Engineering, IIT Delhi. I am working in the area of Program Verification and Compiler Design.
I joined here in July 2016. Prior to this I was working at Jaypee University of Information Technology, Solan H.P. as Assistant Professor in the Department of Computer Science & Engineering.
I completed my masters through an integrated B.Tech-M.Tech in Computer Science from Jaypee Institute of Information Technology, Noida, U.P.
Currently Working On
Course(s): COL750 Foundations of Automatic Verification
T.A. for: COL765 Introduction to Logic and Functional Programming

Majorly I am working towards figuring out a nice topic for my Ph.D. So, basically lots of literature survey.
On the side I'm working on 2 projects one on focused compiler optimization and the other on effective model checking.
Member of Vertecs Research Group
Details of VERification, TEsting, Concurrency, Security / Semantics (VERTECS2) research group can be found on it's webpage.
Additionally we meet Wednesday's to discuss publications in top venue's of PL/Systems research, details of which can be found here.
I am also leading a discussion session series on Baier, Christel, Joost-Pieter Katoen, and Kim Guldstrand Larsen. Principles of model checking. MIT press, 2008.
Sanjana Singh, and Sandeep K. Singh. "A novel approach for bug localization for Exception Handling and Multithreading through mutation."2015 Annual IEEE India Conference (INDICON). IEEE, 2015.
Workshops, Programs & Visits
Japan-Asia Youth Exchange Program in Science (SAKURA)
25 June - 15 July 2017
University of Tokyo
SAKURA is a program for enhancing exchanges between Asia and Japan aiming at future close collaboration of industry-academia-government by facilitating short-term visits to Japan. You can read about my experience.

The First Indian SAT+SMT School
4-10 December 2016
The workshop included a basic course on logic, tutorials on solvers by eminent scientists and developers from around the world, and latest research and applications centered around these solvers.
M.Tech. Dissertation
Bug Localization for Exception Handling and Multithreading
Created a prototype tool for a bug localization technique that is based on the hypothesis that a mutant of the source code could be a better approximation of the intended code. The work involved proposal of mutation operators to create mutants to detect buggy lines of code. And testing of proposed mutants for usefulness towards the hypothesis.

B.Tech. Project
Mining mailing list for extracting useful information
Created a query response system that mines developer mailing lists for extracting useful information and possible response to the query and finally producing the best fit match for a user’s query. Used concepts like caching (of frequent responses), stopword elimination and stemming (for refining query), topic modeling (to classify mails in mailer list), sentiment analysis (to marks mails as positive or negative) and ranking mechanism (for ranking the responses).
Courses enrolled at IIT, Delhi
COL765 Introduction to Logic and Functional Programming
COL730 Parallel Programming
COL729 Compiler Optimizations (Sit through)
COL633 Resource Management in Computer Science
COL750 Foundations of Automatic Verification (Currently Registered)
COL869 Spl. Topics in Concurrency
COV882 Spl. Module in Software Systems
Teaching Assistantship at IIT, Delhi
COL765 Introduction to Logic and Functional Programming​ (Jul-Dec '17)
COL380 Introduction to Parallel and Distributed Programming​ (Jan-May '17)
COL729 Compiler Optimizations (Jul-Dec '16)

©2017 Sanjana Singh