Book Chapters

  1. Debug Data Reduction Techniques,
    Sandeep Chandran and Preeti Ranjan Panda, in Post-silicon Validation and Debug,
    Eds. Prabhat Mishra and Farimah Farahmandi, Springer, 2018

Journals

  1. Managing Trace Summaries to Minimize Stalls During Post-silicon Validation,
    Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharya, Deepak Chauhan, Sharad Kumar, in IEEE Transactions on VLSI Systems (TVLSI), Volume 25, Issue 6, June 2017 (pdf)
  2. Area-aware Cache Update Trackers for Post-silicon Validation,
    Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda, in IEEE Transactions on VLSI Systems (TVLSI), Volume 24, Issue 5, May 2016 (pdf)
  3. Architectural Support for Handling Jitter in Shared Memory based Parallel Applications,
    Sandeep Chandran, Prathmesh Kallurkar, Parul Gupta, Smruti R. Sarangi, in IEEE Transactions on Parallel and Distributed Systems (TPDS), Volume 25, Issue 5, May 2014 (pdf)

Conferences

  1. Extending Trace History Through Tapered Summaries in Post-silicon Validation,
    Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Deepak Chauhan, Sharad Kumar, in Asia and South Pacific Design Automation Conference (ASPDAC), Macao SAR, China, 2016 (Best paper award candidate) (pdf)
  2. A Generic Implementation of Barriers using Optical Interconnects,
    Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda and Smruti R. Sarangi, in International Conference On VLSI Design (VLSID16), Kolkata, India, 2016 (pdf)
  3. Space Sensitive Cache Dumping for Post Silicon Validation,
    Sandeep Chandran, Smruti R.Sarangi, Preeti Ranjan Panda, in Design, Automation and Test in Europe (DATE), Grenoble, France, 2013 (pdf)