Assignment: Cross Assembling
You have to translate one instruction set into another. Each student
has been allotted one translation to do. More details will be
available later. You have to also write test programs (they should be
at least involve 2D-arrays) such as matrix multiplication (the obvious
way) to test out your code.
Before you start your design you need to answer the following
questions, for many of which I have no answers and you may have to
surf the net to find answers. More likely you have may have to go to
some outdated repository of information like the Central Library and
look at books on the matter, since most of these architectures predate
Some of the questions may also be such that you may not have actually
learnt them in your architecture courses, but you need to have the
inquisitive mind to find out about them independently through other
sources. After all, not everything related to a subject is taught in
Since the main problem is that of translating assembly programs from
one instruction set (called Source
to another called Target.
All the architectures chosen are 16-bit register architectures, so that
already answers two important questions (What are the questions?).
Questions to be answered
The answers to the above questions may depend on the answers to the following?
- Which instructions in the Source have a direct corresponding instructions
in the Target?
- Which instructions in the Source require more code writing than direct
- Which subset of the target machine instruction set is sufficient for the
purpose of this cross assembler, without compromising on performance?
- Are both the machines byte-addressable or word-addressable or both?
- If it is both, then how many bytes make a word? Is there a difference?
If there is a difference then how will you do alignment?
- Is there an endian-ness that one has to worry about? Do the source
and target have different endian-ness?
- What are the alignment features of the architectures? Are arrays aligned
along word boundaries?
- Are the instruction structures different in the two machines (e.g. 2 operand vs. 3 operand for arithmetic instructions)? If they differ how will you handle the third operand?
- How many registers are available in the two machines?
- Do the two architectures have indexed as well as indirect
addressing? If they are different in this sense, then how will you handle
- What are the word lengths, register lengths and addressing modes in the
two machines? If only the Source allows virtual addressing how will you
simulate that in the Target?
- What are the register and memory underflow and overflow issues? How will
you handle them?
- Is there a facility for setting condition codes in both architectures? If
not how will you handle condition code checking?
- How will you translate conditional and unconditional jumps (especially
- Are there any other important questions that I have left out? If so what
are they and what are your answers to them from a design perspective?