Assignment: Cross Assembling

You have to translate one instruction set into another. Each student has been allotted one translation to do. More details will be available later. You have to also write test programs (they should be at least involve 2D-arrays) such as matrix multiplication (the obvious way) to test out your code. Before you start your design you need to answer the following questions, for many of which I have no answers and you may have to surf the net to find answers. More likely you have may have to go to some outdated repository of information like the Central Library and look at books on the matter, since most of these architectures predate the web. Some of the questions may also be such that you may not have actually learnt them in your architecture courses, but you need to have the inquisitive mind to find out about them independently through other sources. After all, not everything related to a subject is taught in the course. Since the main problem is that of translating assembly programs from one instruction set (called Source to another called Target. All the architectures chosen are 16-bit register architectures, so that already answers two important questions (What are the questions?). Questions to be answered The answers to the above questions may depend on the answers to the following?
  1. Are both the machines byte-addressable or word-addressable or both?
  2. If it is both, then how many bytes make a word? Is there a difference? If there is a difference then how will you do alignment?
  3. Is there an endian-ness that one has to worry about? Do the source and target have different endian-ness?
  4. What are the alignment features of the architectures? Are arrays aligned along word boundaries?
  5. Are the instruction structures different in the two machines (e.g. 2 operand vs. 3 operand for arithmetic instructions)? If they differ how will you handle the third operand?
  6. How many registers are available in the two machines?
  7. Do the two architectures have indexed as well as indirect addressing? If they are different in this sense, then how will you handle this feature?
  8. What are the word lengths, register lengths and addressing modes in the two machines? If only the Source allows virtual addressing how will you simulate that in the Target?
  9. What are the register and memory underflow and overflow issues? How will you handle them?
  10. Is there a facility for setting condition codes in both architectures? If not how will you handle condition code checking?
  11. How will you translate conditional and unconditional jumps (especially forward jumps)?
  12. Are there any other important questions that I have left out? If so what are they and what are your answers to them from a design perspective?
cols 0 1 2 3 4
Row Gp Entry Name Source Target
1 1 2000379 Avinash Prasad PDP-11 IBM360
2 1 2000387 Nitin Singh PDP-11 NS32016
3 1 2000391 Ram Singla PDP-11 r3000-isa
4 1 2001114 Japinder Singh Chawla PDP-11 Z8000
5 1 2001134 R Srivaths r3000-isa 68000
6 1 2001416 Ashwani Kumar PDP-11 9900
7 1 2001468 GAURAV SINHA 68000 9900
8 2 2000376 Ajit 68000 NS32016
9 2 2000388 Pankaj Garg 68000 PDP-11
10 2 2001103 Ankit Gupta 68000 Z8000.txt
11 2 2001135 S Anand 9900 68000
12 2 2001417 Atish Dipankar 9900 8086
13 2 2001425 Ratnesh Kumar 9900 IBM360
14 3 2000135 Siddarth R Chandrasekar IBM360 8086
15 3 2000377 Amit Khemka IBM360 9900
16 3 2001104 Ankur Gupta IBM360 NS32016
17 3 2001120 Mayank Gupta IBM360 PDP-11
18 3 2001124 Nitin Jindal IBM360 r3000-isa
19 3 2001128 Rajat Khare IBM360 Z8000
20 1 2001462 Anurag Khilnani 68000 8086
21 3 2001418 Gurinder Singh NS32016 68000
22 3 2001430 Sunny Ladkani NS32016 9900
23 4 2000378 Anish Bansal NS32016 IBM360
24 4 2000382 Gajinder Singh NS32016 PDP-11
25 3 2001133 Rohitashwa Kumar Meena NS32016 8086
26 4 2001141 Vikrant Chaudhary NS32016 r3000-isa
27 4 2001423 Pranay Pratap NS32016 Z8000
28 4 2001427 Rohit Kumar Bansal PDP-11 68000
29 4 2001431 Vishesh Kumar PDP-11 8086
30 5 2003JVL0019 Mayank Ahuja 9900 NS32016
31 5 2003MCS0013 Gayathri Nair 9900 PDP-11