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Rahul Jain is currently a Phd Scholar at Department of Computer Science and Engineering, Indian Institute of Technology Delhi. His Phd supervisor is Prof Preeti Ranjan Panda. He is the recipient of Prime Ministers Doctoral Fellowship in collaboration with Intel, where he is working closely with Sreenivas Subramoney, Director, Microarchitecture Lab, Intel.

His research interests are Energy Efficient Computing, Low Power Architectures, Power Optimizations and Machine Learning applications to Computer Architecture Optimizations. The title of his thesis is "Machine Learned Machines: Reinforcement Learning Exploration for Architecture Co-optimization". He has recently completed his Phd Synopsis. His research paper at DATE-2016, Germany was nominated for the "Best IP Award".

He has more than 8 years industry experience and has worked at Amazon , Xilinx, Calypto and CoWare, working on different Optimization Problems in various domains. Rahul has completed his M.Tech in VLSI Design (jointly offered by Dept of CSE, EE, CARE) from IIT-Delhi securing a CPGA of 9.4. He was awarded a trophy for “Highest CGPA among outgoing PG students, 2006” from Kumaon House, IIT-Delhi. He was actively involved in the research activities at IIT-Delhi and has four publications in leading IEEE International Conferences during his M.Tech. He has a good programming background and was ranked 6th in "The ACM Asia Programming Contest", IIT Kanpur, 2002. His B.Tech is in Information Technology and he scored 99.23 Percentile in GATE-2003 Computer Science. He is a merit scholarship holder throughout his B.Tech and M.Tech program.

  • Research

    We plan to study how different individual power-saving mechanisms interact with respect to the extent of power saved and degree of performance compromised, and ultimately, arrive at a practical strategy for selecting the combination of the different techniques that satisfies a given power budget, and delivers the maximum performance within that budget. The joint impact of multiple power-saving strategies would be studied first, and inferences made there would be used in a second phase to propose and validate a high-level strategy on the optimal responses by the run-time system, which would be a combination of one or more individual mechanisms.
    The effect of applying multiple optimizations is not always additive, and this makes this problem complex. We have found Reinforcement Learning to be very effective in handling such complexities. We are using the Sniper Simulator with pybrain as the machine learning library

    • Patents

      • Rahul Jain , Preeti Ranjan Panda, Sreenivas Subramoney
        Dynamic Cache Co-partitioning by Machine Learned Caches
        To be Filed by March 2017 by Intel Technologies at US Patent and Trademark Office
      • Rahul Jain , Preeti Ranjan Panda, Sreenivas Subramoney
        Reinforcement Learning based Adaptive Co-optimization of Cores, LLC and On-chip Network
        Filed in March 2016 by Intel Technologies at US Patent and Trademark Office
    • International Conferences and Journals

      For the published versions, please visit the website of the publisher. All the copyrights belong to the respective publishers.

      • Rahul Jain , Preeti Ranjan Panda, Sreenivas Subramoney
        Cooperative Multi-Agent Reinforcement Learning based Co-optimization of Cores, Caches, and On-chip Network
        ACM Transactions on Architecture and Code Optimization (TACO)
        Submitted
      • Rahul Jain , Preeti Ranjan Panda, Sreenivas Subramoney
        A Coordinated Multi-Agent Reinforcement Learning Approach to Multi-Level Cache Co-partitioning
        International IEEE/ACM Design, Automation, and Test in Europe (DATE-2017) [pdf]
        (Accepted) March 2017, (<25% acceptance rate)
      • Rahul Jain , Preeti Ranjan Panda, Sreenivas Subramoney
        Machine Learned Machines: Adaptive Co-optimization of Caches, Cores, and On-chip Network
        International IEEE/ACM Design, Automation, and Test in Europe (DATE-2016) [pdf]
        "Best IP Award" Nomination
        March 2016
      • Rahul Jain , Preeti Ranjan Panda
        An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform
        Intl. Symposium on Circuits and Systems (ISCAS'07)
        May 2007
      • Rahul Jain , Preeti Ranjan Panda
        An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform(Link)
        Intl. Conference on VLSI Design and Embedded Systems (VLSID'07)
        January 2007
      • Rahul Jain , Preeti Ranjan Panda
        A Power Efficient Architecture for 2-D Discrete Wavelet Transform
        10th IEEE VLSI Design and Test Symposium
        August 2006
      • Rahul Jain , Anindita Mukherjee, Kolin Paul
        Defect-Aware Design Paradigm for Reconfigurable Architectures
        IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006)
        April 2006
    • Academic Forums

      • Machine Learned Machines: Co-optimizing Caches, Cores, and On-chip Network
        10th Inter-Research-Institute Student Seminar in Computer Science 2016, ACM India
        January 2016
      • Runtime System Adaptation for Optimal Energy-Performance Trade-off
        Invited Poster at Intel India Academic Forum 2015
        October 2015
  • Academic Qualifications

    • Doctor of Philosophy (Ph.D.)
      Department of CSE, Indian Institute of Technology, Delhi
      With in collaboration with Intel Microarchitecture Labs
      Prime Minister's Doctoral Fellowship
      CGPA: 10/10
      Feb 2014 –
    • M.Tech, VDTT (Dept of Computer Science)
      Indian Institute of Technology, Delhi
      Industry Scholarship from Cypress Semiconductors, Bangalore
      CGPA: 9.4/10
      2004 - 2006
    • B.Tech, Information Technology
      University School of Information Technology, Guru Gobind Singh Indraprastha University
      Merit Scholarship Holder for all 4-Years
      1999 - 2003
  • Achievements and Awards

    • "Best IP Award" Nomination at DATE-2016
      For the research paper titled: "Machine Learned Machines: Adaptive Co-optimization of Caches, Cores, and On-chip Network"
      March 2016
    • Prime Minster's Fellowship for Doctoral Research
      Confederation of Indian Industry, SERB (Department of Science and Technology), Govt of India
      Industry Sponser: Intel
      April 2014
    • Reached the finals of online rounds of Facebook Hackers Cup-2011
      Facebook
      February 2011
    • Trophy for “Highest CGPA among outgoing PG students, 2006” from Kumaon House
      IIT Delhi
      June 2004
    • Merit Scholarship holder for full M.Tech program at IIT-Delhi
      Cypress Semiconductors
      May 2006
    • Merit scholarship holder throughout B.Tech
      GGS Indraprastha University
      July 1999
    • Ranked 6th in "The ACM Asia Programming Contest", IIT Kanpur
      ACM ICPC
      2002
    • 99.23 percentile GATE Computer Science
      2003
  • Industry Experience

    • AMAZON

        Software Development Engineer-II (Backend-Engineer) , Jan 2012 - 2014

        Worked in the Amazon Webstore Product Team. Webstore is a self service ecoomerce website solution where anyone can create their own ecommerce website with Amazon Infrastructre at the backend. As part of Product Catalog Manager team, I worked on Search Optimization for the 100 million products in the catalog. We worked on better Catalog Search Architecture and Solution based on ElasticSearch solution. I was also part of the Internationalization team where we modified the Google Closure Compiler to automate the legacy javascripti code internationalization.
        Key Technologies: Java, python, NOSql, AWS, S3, SimpleDb, DynamoDb, SQS, Google Closure Compiler, Solr, Lucene, ElasticSearch, AWS CloudSearch

    • Xilinx

        Senior Software Engineer, R&D Software Products, September 2010 – January 2012

        Worked in the Xilinx Synthesis Technology with the focus on Back-end Optimizations. Synthesis Technology is a Hardware Compiler (similar to a software compiler which compiles a high level language like C++ into a executable program), which compiles a high level hardware specification in VHDL, Verilog etc into a Xilinx Gate Level Netlist to be implemented on a FPGA fabric.

    • Calypto Design Systems (acquired by Mentor Graphics)

        Senior Member of Technical Staff, May 2007 – August 2010

        Worked as part of the core technology team of the PowerPro product on the RTL level Power Optimization. Proposed and implemented various Clock Gating and Memory Gating techniques for better power savings. Owned and implemented a Simulation-based RTL power optimization product working with the CTO and enabling the customers towards better optimization decisions. This product was like a valgrind for finding power saving potential in the design.

    • CoWare (acquired by Synopsys)

        Member Technical Staff, May 2006 – April 2007

        As part of the IP Development team for Virtual Platforms, developed various different IP modules for System Level Interconnects