Current PhD Students
Sandeep Chandran (Jointly supervised by Smruti R. Sarangi)
Rahul Jain
Neetu Jindal (Jointly supervised by Smruti R. Sarangi)
Hadi Brais
Lokesh Siddhu
Sakshi Tiwari
Graduated PhD Students
Prasenjit Chakraborty (2015. Now at Intel.)
Namita Sharma (2015. Now at Intel.)
Vaibhav Jain (2015. Now at DAVV. Jointly supervised by Anshul Kumar.)
Krishnaiah Gummidipudi (2013. Now at Intel. Jointly supervised by Anshul Kumar.)
B. V. N. Silpa (2012. Now at Nvidia.)
Neeraj Goel (2012. Now at Synopsys. Jointly supervised by Anshul Kumar.)
Anant Vishnoi (2010. Now at Cadence. Jointly supervised by M. Balakrishnan.)
Aryabartta Sahu (2010. Now at IIT Guwahati. Jointly supervised by M. Balakrishnan.)
Research

Post-silicon Validation

Collaborator: Freescale and Semiconductor Research Corporation (SRC)

As the computer industry moves towards the era of multi-core and many-core SoCs with a large number of processor cores and accelerators, there is an urgent need for revamping the post-silicon validation methodologies, and re-architecting the hardware debug mechanisms. Robust validation methodologies play a vital role in the chip design flow, as the industry struggles to contain costs under increasing design complexity. In this research we attempt a scalable debug methodology that anticipates a large number of cores, and is sensitive to the associated requirements of handling large amounts of debug data with area constraints.

Energy-efficient Computing

Collaborator: Intel

Energy efficiency needs to be built into modern computer systems spanning across the spectrum from embedded systems to server machines, leading to a trade-off involving both performance and energy. We have employed techniques derived from machine learning to perform a fine-grained adjustment of several system components such as caches and NoC. Apart from the standard knobs such as voltage and frequency, we also exploit the configurability provided in modern hardware resources in terms of adjustable cache and on-chip network parameters. Our book Power-efficient System Design surveys power-efficiency and energy-efficiency at different abstraction levels in computing systems.

Memory Exploration and Optimisation

Collaborators: IBM, IMEC

In earlier work, we introduced the concept of Scratch Pad Memory (SPM) and investigated ways to partition on-chip data memory space between scratch pad memory and data cache. The book Memory issues in Embedded Systems-on-chip captures some of the recent developments on data memory optimisations in embedded systems. Our paper Data and memory optimization techniques for embedded systems (ACM TODAES, Apr 2001) has been the most downloaded paper of the journal for several years. As memory technologies evolve, we continue to investigate different ensuing system-level research problems: software caches, data layout, SPM with vector registers, phase change memory, etc.

Other Research Topics

  • Power-efficiency in Graphics Processors
  • Accelerating NoC Emulation
  • High-level Synthesis
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