NEWS
[Nov 2016] Research paper "A Coordinated Multi-Agent Reinforcement Learning Approach to Multi-Level Cache Co-partitioning" by Rahul Jain, P. R. Panda, and S. Subramoney, accepted for presentation at DATE'17, Lausanne.
[Nov 2016] Research paper "Reusing Trace Buffers to Enhance Cache Performance" by Neetu Jindal, P. R. Panda, and S. R. Sarangi, accepted for presentation at DATE'17, Lausanne.
[May 2016] Research paper "Partitioning and Data Mapping in Reconfigurable Cache and Scratch Pad Memory based Architectures" by P. Chakraborty, P. R. Panda, and S.Sen accepted for publication in ACM Transactions on Design Automation of Electronic Systems.
[Mar 2016] Research paper "Machine Learned Machines: Adaptive Co-optimization of Caches, Cores, and On-chip Network" by R. Jain, P. R. Panda, and S. Subramoney, receives Best Interactive Presentation nomination at DATE'16, Dresden.
[Jan 2016] Research paper "Extending Trace History Through Tapered Summaries in Post-silicon Validation" by S. Chandran, P. R. Panda, S. R. Sarangi, D. Chauhan, and S. Kumar, receives Best Paper nomination at ASPDAC'16, Macau.
[Jan 2016] Prof. Chita Das from Penn State Univ. visits the dept. and delivers a seminar on "Architecting Next-Generation Mobile Platforms".
[Jan 2016] P. R. Panda was a member of the panel discussing "The Changing Indian Landscape, and Implications to University-Industry Collaboration" at Semiconductor Research Consortium India Design Review 2016, Bangalore.
[Jan 2016] Sandeep presented the research paper "A Generic Implementation of Barriers using Optical Interconnects" by S. Chandran, E. Peter, P. R. Panda, S. R. Sarangi, at VLSI Design'16, Kolkata.
[Jan 2016] P. R. Panda is an Associate Editor of IEEE Embedded Systems Letters starting 2016.
[Dec 2015] Research paper "Area-Aware Cache Update Trackers for Postsilicon Validation" by S. Chandran, S. R. Sarangi, and P. R. Panda, to appear in IEEE Transactions on VLSI Systems.
[Oct 2015] Research paper "Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures" by I. Filippopoulos, N. Sharma, P. G. Kjeldsberg, F. Catthoor, P. R. Panda to appear in ACM Transactions on Embedded Computing Systems.
[Oct 2015] Namita Sharma and Prasenjit Chakraborty are conferred the PhD degree.
[Oct 2015] Namita Sharma and P. R. Panda attend ESWeek 2015, Amsterdam. Namita presents the research paper "Energy Efficient FFT Implementation through Stage Skipping and Merging" by N. Sharma, P. R. Panda, and F. Catthoor.
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Preeti Ranjan Panda
Professor, Dept. of CSE, IIT Delhi
I am a Professor of Computer Science and Engineering at IIT Delhi. My research interests are in the areas of:
  • Embedded Systems
  • Memory Exploration and Optimisation
  • Energy-efficient Computing
  • Electronic Design Automation and Design Methodology
Our research group investigates several research problems that arise at the intersection of Embedded Systems and the adjacent areas of Computer Architecture, Compilers, and Systems-on-Chip design. How do we save energy while not sacrificing performance in computing systems? How do we restructure data and computation to take advantage of power optimisation opportunities? What are the system-level implications of modern generations of memories? What architectural features can we add to modern processors and systems-on-chip for enhancing system debug and validation?
Books
Book Cover: Power-efficient System Design Power-efficient System Design
Preeti Ranjan Panda, Aviral Shrivastava, B. V. N. Silpa, Krishnaiah Gummidipudi
Springer, New York, 2010.
Book Cover: Memory Issues in Embedded Systems-On-Chip: Optimizations and
Exploration Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
Kluwer Academic Publishers, Norwell, 1999.
Copyright (C) 2016 P. R. Panda
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