Research Interest

Exploration of memory hierarchy in high issue rate processors.

With the advance in VLSI, dimensions are shrinking, more transistors per chip are available for computation, higher clock rate processors are available. But this increasing clock frequencies is non-uniform over processors and peripherals like memory. Memory bandwidth and access time become a bottleneck for current/future processors architecture. Most of the applications like multi-media, network require very high bandwidth of memory.

The above mentioned problem is dealt with various method but we are dealing with a specific case of high issue processors. In high issue rate processors, many instructions are issues simultaneously. Example architectures of high issue rate processors are VLIW and superscalar and example processors are Itenium, Trimedia, Alpha21264. Current many of state of art processors are using 8 issue VLIW processor. It is well known that memory instruction are considerable portion of total number of instructions. So there will be more then one memory load store require per VLIW instruction. Concurrent loads can be handled using multiport memory. But in multiport memory area increase N3, delay increases N3/2 and power increase N3. Various architectural and device level methods are suggested for the problem. Some of them are increasing the number of banks and then use cross-bars switches. Function units are first clustered then one cache is associated with each cluster in inter-leave manner. In this case a bus is required to handle misses in the local cache. Synchronization protocols are required similar to multi-processor cache. Some people suggest one more level of the cache. There can be small buffers in each of the cluster. This small buffer decrease the number of references to unified cache.

Publications
  • Power Reduction in VLIW Processor with Compiler Driven Bypass Network
    Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
    In Int Conference in VLSI Design and Embedded System(VLSI 2007), Bangalore, India, January 2007.

Low Power Design, Modeling and Estimation

Low power has become a major challange for VLSI design in future technologies. Low power design techniques are available at different stages of design, algorithmic level, behavior level, circuit and layout level. We are interested in algorithmic and architectural level low power techniques. For this goal we need to do behavior modeling of application and power estimation at behaviour level.

Publications
  • Energy Based Design Space Exploration of Multiprocessor VLIW Architectures
    Manoj Gupta, Mayank Gupta, Neeraj Goel, M.Balakrishnan
    In 10th Euromicro conference on Digital System Designa (DSD 2007), Lu beck, Germany, August 2007

Reconfigurable Computing and FPGA Prototyping

RC is a tool that can be of interest in future. Some of the commercial FPGA vendors provide run time reconfigurability in their devices. Our initial goal is to test RC in the FPGA devices and explore where it can be used effectively.

Publications
  • Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture
    Neeraj Goel, Kolin Paul
    In 15th International Conference on Advanced Computing and Communication, Guwahati, India, December 2007

  • Fault Tolrents FPGA using Redundant Columns
    Neeraj Goel, Kolin Paul
    In Proc of VLSI Design and Test Synposium(VDAT 2006), Goa, India, August 2006

  • Partial and Dynamic Reconfiguration in Xilinx FPGAs - A Quantitative Study
    Harsh Dhand, Neeraj Goel, Mukesh C Aggarwal, Kolin Paul
    In Proc of VLSI Design And Test Symposium(VDAT 2005), Banglore, India, August 2005

Details of current projects, work etc. on Group Webpage
Embedded System Group

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