PhD Research Problem:

• Runtime Mapping of Application(s) onto Reconfigurable Coarse-Grained Arrays

Supervisors:

• M. Balakrishnan, Professor, CSE Dept, IIT Delhi.
• Kolin Paul, Associate professor, CSE Dept., IIT Delhi.

Research Interest:

• Computer arcitecture, multi-processing platforms, reconfigurable architectures, software-hardware co-design, application mapping, and Optimization.

Research Done:

1. Literature survey on mapping application task graph onto multi-processing reconfigurable platforms
2. Experiments on Daedalus framework to map application task graph onto MPSoC, along suggestions to improve it for runtime reconfiguration
3. High speed implementation of JPEG Encoder on reMORPH array
4. Runtime Reconfiguration implementation of JPEG Encoder, Huffman Coding, JPEG 2000 Decoder on MicroBlaze array
5. Optimal mapping formulation and implementation, using TOMLAB/CPLEX in MATLAB, targeting:
   • Applications with acyclic task graph
   • Applications with cyclic task graph
   • Homogneous 2D multi-grain platforms with mesh topology
   • Homogneous 3D multi-grain platforms with mesh topology
   • Homogeneous multi-grain platforms with any arbitrary interconect topology
   • Heterogeneous multi-grain platforms with any arbitrary interconnect topology
6. Runtime reconfiguration flow and handshaking procedure
7. MicroBlaze codebase design for runtime partial reconfiguration

Publications:

1. Mansureh S. Moghaddam, M. Balakrishnan and Kolin Paul, "Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform", 11th Intel. Symposium in Applied reconfigurable Computing (ARC'15), Bocum, Germany, 2015. (pdf)


2. Mansureh S. Moghaddam, M. Balakrishnan and Kolin Paul, "Optimal Runtime Task Mapping to a Partially Reconfigurable Coarse-Grained Array", 9th Intel-Research-Institute Student Seminar in Computer Science (IRISS'15), Goa, India, 2015. (pdf)


3. Mansureh S. Moghaddam, Kolin Paul and M. Balakrishnan, "Mapping Tasks to a Dynamically reconfigurable Coarse-Grained Array", 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'14), Boston, MA, USA, 2014. (pdf)


4. Mansureh S. Moghaddam, Kolin Paul and M. Balakrishnan, "Design and Implementation of high Performance Architectures with Partially Reconfigurable CGRAs", the 20th Reconfigurable Architectures Workshop (RAW'13), Boston, MA, USA, 2013. (pdf)


5. Kolin Paul, Chinmaya Dash and Mansureh S. Moghaddam, "reMORPH -- A Runtime Reconfigurable Architecture", 15th Euromicro Conference on Digital System Design (DSD'12), Cesme, Izmir, Turkey, 2012. (pdf)


6. Nicolas Sklavos and Mansureh S. Moghaddam, "Rabbit Data Streaming: Architecture & FPGA Implementation", 3rd Iranian Society of Cryptology Conference (ISCC'05), Isfahan University of Technology, Isfahan, Iran, 2005. (pdf)


7. Mansureh S. Moghaddam, "Implementation Aspects of Rijndael Encryption Algorithm", International Electrical Conference on Computer Security (IeCCS'05), Athen, Greece, 2005. (pdf)

Course Work Experience:

• PhD Course Work:

  • CSL633/373 - Resource Management in Computer Systems (instructor Dr. Sorav Bansal).
  • CSL630 - Advanced Data Structures (instructor: Prof. S. N. Maheswari).
  • CSL718 - Architecture of High Performance Systems (instructor: Dr. Kolin Paul).
  • CSL719 - Synthesis of Digital Systems (instructor: Prof. Preeti Ranjan Panda).
  • HUL810 - Communication Skills

• Teaching Assistantship:

  • COL100: Introduction to Computer Science
  • CSL102: Introduction to computer science
  • CSL633/373: Operating System/resource Management
  • CSL316: Digital System design

• Teaching Experience Before Joining IITD:

  • Computer System Architecture
  • Digital System design
  • 80x86 Micro processors
  • Micro Controllers; Architecture and Programming
  • 80x86 Assembly Language Programming
  • Interfacing Circuits and Chips
  • FPGA Chips and VHDL Programming
  • C/C++ Programming Language

Skills:

• Softwares: C/C++, Xilinx ISE Design Suite , Xilinx Embedded Development Kit (EDK), gnuplot, excel, VHDL, Perl, python, Matlab, TOMLAB/CPLEX Optimization Toolset, Unix, SML, Latex, Unix Network programming, HTML, Daedalus Framework


• Operation systems: WINDOWS 7, UNIX, open source PIOS, open source PINTOS


• Hardware: Xilinx FPGA boards (XUPV2, XUPV5, ML605, Atlys), Xilinx FPGA devices (Spartan, Virtex 4, virtex 5 and virtex 6), MicroBlaze, Micro Controllers (e.g. AVR, 8051), Micro processors (e.g. Intel 80x86 and interfacing chips)

Hobbies:

• reading, badminton, ping pong, watching movies, cooking