# random number generator seed (0 for timer seed)
-seed                             1

# instruction fetch queue size (in insts)
-fetch:ifqsize                    4

# extra branch mis-prediction latency
-fetch:mplat                      3

# branch predictor type {nottaken|taken|perfect|bimod|2lev}
-bpred                        bimod

# bimodal predictor BTB size
-bpred:bimod                   2048

# 2-level predictor config (<l1size> <l2size> <hist_size>)
-bpred:2lev            1 1024 8

# instruction decode B/W (insts/cycle)
-decode:width                     4

# instruction issue B/W (insts/cycle)
-issue:width                      4

# run pipeline with in-order issue
-issue:inorder                false

# issue instructions down wrong execution paths
-issue:wrongpath               true

# register update unit (RUU) size
-ruu:size                        16

# load/store queue (LSQ) size
-lsq:size                         8

# l1 data cache config, i.e., {<config>|none}
-cache:dl1             dl1:128:32:4:l

# l1 data cache hit latency (in cycles)
-cache:dl1lat                     1

# l2 data cache config, i.e., {<config>|none}
-cache:dl2             ul2:1024:64:4:l

# l2 data cache hit latency (in cycles)
-cache:dl2lat                     6

# l1 inst cache config, i.e., {<config>|dl1|dl2|none}
-cache:il1             il1:512:32:1:l

# l1 instruction cache hit latency (in cycles)
-cache:il1lat                     1

# l2 instruction cache config, i.e., {<config>|dl2|none}
-cache:il2                      dl2

# l2 instruction cache hit latency (in cycles)
-cache:il2lat                     6

# flush caches on system calls
-cache:flush                  false

# convert 64-bit inst addresses to 32-bit inst equivalents
-cache:icompress              false

# memory access latency (<first_chunk> <inter_chunk>)
-mem:lat               18 2

# memory access bus width (in bytes)
-mem:width                        8

# instruction TLB config, i.e., {<config>|none}
-tlb:itlb              itlb:16:4096:4:l

# data TLB config, i.e., {<config>|none}
-tlb:dtlb              dtlb:32:4096:4:l

# inst/data TLB miss latency (in cycles)
-tlb:lat                         30

# total number of integer ALU's available
-res:ialu                         4

# total number of integer multiplier/dividers available
-res:imult                        1

# total number of memory system ports available (to CPU)
-res:memport                      2

# total number of floating point ALU's available
-res:fpalu                        4

# total number of floating point multiplier/dividers available
-res:fpmult                       1

# operate in backward-compatible bugs mode (for testing only)
-bugcompat                    false
 
 

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