NAME
MANOJ   KUMAR   JAIN

ENTRY No.
[1999 RCS 002]

S.G.P.A.
N.A.

C.G.P.A.
8.0
 

As per research plan we have developed a framework for exploring register file size in application specific instruction set processors or ASIPs. Implementation and validation of our framework is done. Our framework shown very encouraging results. We have validated the framework for the processor ARM7TDMI. Results produced have an average error of about 10% which is smaller comparing to the avaerage error (29%) produced by a compiler based framework encc been developed at university of Dortmund, Germany. Our framework is significantly faster compared to encc. I have also submitted and presented a paper in IRISS 2002 (inter research institutes students seminars) being held at IISc. Bangalore during 28th March 2002 and 29th March 2002 [1].

Some of the important features of our framework are as follows.

• No code generation is required (whereas most of the approaches consider register allocation and instruction scheduling for generating correct and efficient code).
• Trace file is not generated.
• We want to ensure the best possible use of registers so register allocation is performed directly on the dependency graph generated from the application, using SUIF IR of the application. No other resource constraints are considered at this stage, ensuring the best possible use of registers. Scheduling is done using a resource constraint list scheduling after the register allocation is done to find the actual performance. Schedule estimates are generated using the execution count of the basic block generated from the profiler.
• If only overhead estimates can guide the register file size evaluation, then scheduling is not at all required.
• Option of spilling a variable in to memory and loading back when it is required is considered.
• Global needs are taken care of.
• Only register allocation is performed, no register assignment is done.
• Very simple processor description, mainly operation latency values along with the range of register (maximum number of registers to be considered) is taken in the input.
• Framework is retargetable. Only simple parameters and latencies defined in the description file needs to be changed.
• Fast compared to compiler-simulator based framework.
• Process is fully automated.

References

1. Jain M.K. : `` Exploring Register File Size in ASIP Synthesis.'', Inter Research Institutes Students Seminars, IRISS 2002, March 28-29 2002, IISc. Bangalore.
2. Wehmeyer L.; Jain M.K.; Steinke, S.; Marwedel P.; Balakrishnan, M. : ``Analysis of the Influence of Register File Size on Energy Consumption, Code Size and Execution Time.'', IEEE TCAD, vol. 20, no. 11, Nov. 2001.
3. Jain M.K.; Wehmeyer L.; Steinke, S.; Marwedel P.; Balakrishnan, M. : ``Evaluating Register File Size in ASIP Design.'', Proceedings of the Ninth International Symposium on Hardware/ Software Codesign, CODES 2001, 25-27 April, 2001, Copenhagen, Denmark, Pages: 109-114.
4. Wehmeyer L.; Jain M.K.; Steinke, S.; Marwedel P.; Balakrishnan, M. : ``Using an Energy Aware Compiler Framework to Evaluate Changes in Register File Size towards ASIP-Design.'', Fifth International Workshop on Software and Compilers for Embedded Systems, SCOPES 2001, 20-22 March, 2001, St. Goar, Germany.
5. Jain, M.K.; Balakrishnan, M.; Anshul Kumar : ``ASIP Design Methodologies : Survey and Issues.'', Proceedings of the Fourteenth International Conference on VLSI Design, 2001, 3-7 Jan. 2001, Pages: 76-81.
6. Jain M.K.; Wehmeyer L.; Marwedel P.; Balakrishnan, M. : ``Register File Synthesis in ASIP Design.'', Technical Report #746 07.12.200, Lehrstuhl Informatik XII, University of Dortmund, Germany.
7. Jain, M. K.; Balakrishnan, M.; Anshul Kumar : ``ASIP Design Methodologies : Survey and Issues.'', Technical Report TR #2000/23, Embedded System Project, Department of Computer Science and Engineering, Indian Institute of Technology, Delhi.

Progress Reports
 
 
 

site last updated on
May 15, 2002 by Manoj Kumar Jain