Publications

 
 

Complete List of Publications (in chronological Order)


Books


  1. 1.Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications, Sharat Chandra Varma Bogaraju, Kolin Paul, M Balakrishnan, Springer ISBN 978-981-10-0589-3 April 2016

Refereed Journals


  1. 1.Avval Gupta, Anju Kansal, Kolin Paul and Sanjiva Prasad, ``A Modular Android based Multi Sensor mHealth System" Springer Communications in Computer and Information Science Volume 511 of the series Communications in Computer and Information Science pp 360-377 January 2016

  2. 2.Niladri Tripathi, I N Kar and Kolin Paul, ``Model Based Robust Control Law for Linear Event-triggered System", Asian Journal of Control December 2015 (online) DOI: 10.1002/asjc.1276

  3. 3.Rajesh Kumar Pal, Ierum Shanaya, Kolin Paul and Sanjiva Prasad,  ``Dynamic Core Allocation for Energy-Efficient Video Decoding on Embedded Multicore Platforms", Future Generation Computer Systems  Springer 56, 247-261, 2016

  4. 4.Tripathi M, Deo RC, Suri A, Srivastav V, Baby B, Kumar S, Kalra P, Banerjee S, Prasad S, Paul K, Roy TS, Lalwani S. ``Design and Validation of an Open Source Partial Task Trainer for Endonasal Neuro-endoscopic Skills Development: Indian Experience", World Neurosurgery. 2016 Feb;86:259-69. doi: 10.1016/j.wneu.2015.09.045. Epub 2015 Sep 26.

  5. 5.Sharat Chandra Varma Bogaraju, Kolin Paul, Balakrishnan M, Dominique Lavenier, ``Hardware Acceleration of De Novo Genome Assembly", International Journal of Embedded Systems, Special Issue on Reconfigurable Architectures and Self-Adaptive Autonomic Systems, to appear, 2016

  6. 6.Arun Parakh, M. Balakrishnan, Kolin Paul,``Improving Map-Reduce for GPUs with cache",  International Journal of High Performance System Architecture (IJHPSA) Volume 5 Issue 3, July 2015

  7. 7.Syed Mohammad Asad Hassan Jafri,  Ahmed Hemani, Kolin Paul, ,Juha Plosila  and Hannu Tenhunen ``Polymorphic Configuration Architecture for Coarse Grained Reconfigurable Architectures" IEEE Transactions on Very Large Scale Integration (VLSI) Systems   Page 403-407 Jan. 2016

  8. 8. Syed Mohammad Asad Hassan Jafri, Ozan Ozbag, Nasim Farahini,  Ahmed Hemani, Kolin Paul, Juha Plosila  and Hannu Tenhunen ``Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling on CGRAs" ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Neuromorphic Computing and Emerging Many-Core Systems for Exascale Computing, Volume 11 Issue 4, April 2015

  9. 9.Anusha Subhramony Iyer and Kolin Paul, ``Self-Assembly: A Review of Scope and Applications" IET Nanobiotechnology. June 2015 ;9(3):122-35.

  10. 10.Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Kolin Paul ``Parallel Distributed Scalable Address Generation Scheme for a Coarse Grain Reconfigurable Computation and Storage Fabric", Microprocessors and Microsystems - Embedded Hardware Design 38(8): 788-802 (2014)

  11. 11.Rajesh Kumar Pal, Kolin Paul and Sanjiva Prasad, ``A High Performance Reconfigurable ManyCore Architecture",  J. Parallel Distrib. Comput. 74(11): 3071-3086 (2014)

  12. 12.Manish Kumar Jaiswal, Ray C.C. Cheung, M. Balakrishnan and Kolin Paul, ``Unified Architecture for Double / Two-Parallel Single Precision Floating Point Adder",  IEEE Trans. on Circuits and Systems 61-II(7): 521-525 (2014)

  13. 13.Manish Kumar Jaiswal, Ray C.C. Cheung, M. Balakrishnan and Kolin Paul,  ``Series Expansion based Efficient Architectures for Double Precision Floating Point Division",  Journal of Circuits, Systems and Signal Processing. November 2014, Volume 33, Issue 11, pp 3499-3526.

  14. 14.Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Kolin Paul, Ahmed Hemani, Juha Plosila  and Hannu Tenhunen, ``Private configuration environments (PCE) for efficient reconfiguration, in CGRAs", Springer Design and Automation of Embedded Systems, 2014.

  15. 15.Syed Mohammad Asad Hassan Jafri, Liang Guang, Ahmed Hemani, Juha Plosila, Kolin Paul and Hannu Tenhunen, ``Energy-aware Fault-tolerant Network-on-chips for Addressing Multiple Traffic Classes", Microprocessors and Microsystems - Embedded Hardware Design 37(8-A): 811-822 (2013)

  16. 16.Ashish Suri, Martin Bettag, Manjul Tripathi, Rama Chandra Deo, Tara Sankar Roy, Sanjeev Lalwani, Christoph Busert, Marcus Mehlitz, Payal Jotwani, Britty Baby, Vinkle Srivastav, Ramandeep Singh, Subodh Kumar, Prem Kalra, Subhashis Banerjee, Kolin Paul, Sanjiva Prasad, Bhawani Sharma. ``Simulation in Neurosurgery in India- NETS" CNS Quarterly, Summer 2014

  17. 17.Tripathi M, Deo RC, Suri A, Srivastav V, Baby B, Kumar S, Kalra P, Banerjee S, Prasad S, Paul K, Roy TS, Lalwani S. "Quantitative Analysis of Kawase's Triangle versus Modified Dolenc Kawase Rhomboid Approach for Middle Cranial Fossa Lesions with Variable Antero-posterior Extension". Journal of  Neurosurg  Jul 2015;123(1):14-22. doi: 10.3171/2015.2.JNS132876. Epub 2015 Apr 3.

  18. 18.Jotwani P, Srivastav V, Tripathi M, Deo RC, Baby B, Damodaran N, Singh R, Suri A, Bettag M, Roy TS, Busert C, Mehlitz M, Lalwani S, Garg K, Paul K, Prasad S, Banerjee S, Kalra P, Kumar S, Sharma BS, Mahapatra AK. "Free-access Open-source e-Learning in Comprehensive Neurosurgery Skills Training". Neurology India,  Jul-Aug 2014 ;62(4):352-61. doi: 10.4103/0028-3886.141208.

  19. 19.Tapas Kumar Kundu, Kolin Paul, "Improving Android Performance and Energy Efficiency," JOLPE Volume 7, Number 4, December 2011

  20. 20.Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata. ACM JETC 7(3): 13 2011

  21. 21.R. Devadoss, Kolin Paul, and M. Balakrishnan. Coplanar QCA crossovers. Electron. Letters 45, 1234 (2009)

  22. 22.Kolin Paul, D. R. Chowdhury, and P. P. Chaudhuri, "Theory of Extended Linear Machines", IEEE Transactions on Computers, September 2002.


Journals (under Review)


  1. 1.Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Peter Ellerve, Ahmed Hemani, Kolin Paul, Hannu Tenhunen and Juha Plosila, ``Morphable Compression Architecture for Efficient Configuration in CGRAs", Microprocessors and Microsystems

arXiv


  1. 1.Niladri Sekhar Tripathy, I. N. Kar, Kolin Paul, ``Model Based Robust Control Law for Linear Event-triggered System", arXiv:1412.8365v1



Referred Book Chapters


  1. 1.Kolin Paul and Sanjay Rajopadhye, Back Propagation Algorithm: Achieving 5 GOPS on the Virtex-E" Book Chapter in FPGA Implementations of Neural Networks By Amos R. Omondi; Jagath C. Rajapakse (Eds.). 0-387-28485-0 March, 2006.


Referred Conferences/Workshops


  1. 1.Shalini Singh , Kolin Paul, Geeta   and Sanjiva Prasad, ``prasavGraph: Android based Labor Monitoring" HEALTHINF  2016 Rome, Italy.

  2. 2.Kolin Paul and Vijay Kumar, `` mNetra: Fundus Imaging based Retinoscopy", HEALTHINF 2016  Rome, Italy.

  3. 3.Kolin Paul, Abdul Khalid, Yasoob Haider, Shalini Singh and Sanjiva Prasad, ``prasavGraph: an Android-based e-Partograph", ICSMB India, 2016

  4. 4.Pei Liu, Kolin Paul, Ahmed Hemani, ``3D-stacked Many-Core Architecture for Biological Sequence Analysis Problems", SAMOS 2015 

  5. 5.Rajeswari Devadoss, Kolin Paul and M Balakrishnan, ``An n-input Majority Algebra based Logic Synthesis Tool for Quantum-dot Cellular Automata", IWLS 2015

  6. 6.Kolin Paul, Mansureh S, Kolin Paul M Balakrishnan,``Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform" 11th International Symposium on Applied Reconfigurable Computing  Bochum, Germany 2015

  7. 7.Kolin Paul and Vijay Kumar, `` Fundus Imaging Based Affordable  Eye Care", HEALTHINF 2014 

  8. 8.Niladri Tripathi, I N Kar and Kolin Paul, ``An Event-triggered Based Robust Control of Robot Manipulator", ICARCV 2014 Singapore.

  9. 9.Niladri Tripathi, I N Kar and Kolin Paul, ``A Model Based Robust Control Law for Linear Event-triggered System", INDICON, Pune 2014 

  10. 10.Rajesh Kumar Pal, Kolin Paul and Sanjiva Prasad, ``Energy Efficient Dynamic Core Allocation for Video Decoding in Embedded Multicore Architectures", IEEE ICESS-2014.(

  11. 11.Sharat Chandra Varma Bogaraju, Kolin Paul and M Balakrishnan, ``High Level Design Approach to Accelerate De Novo Genome Assembly using FPGAs", EUROMICRO DSD 2014, Italy.

  12. 12.Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Peter Ellerve, Ahmed Hemani, Kolin Paul, Hannu Tenhunen and Juha Plosila, ``Morphable Compression Architecture for Efficient Configuration in CGRAs", EUROMICRO DSD 2014 Italy 

  13. 13.Syed Mohammad Asad Hassan Jafri, Masoud Daneshtalab, Kolin Paul, Ahmed Hemani, Hannu Tenhunen, Guillerno Serreno and Naeem Abbas ``TransPar: Transformation Based Dynamic Parallelism for Low Power CGRAs", FPL 2014 (

  14. 14.Manish Kumar Jaiswal, Ray C.C. Cheung, M. Balakrishnan and Kolin Paul, ``Configurable Architecture for Double / Two-Parallel Single Precision Floating Point Division", ISVLSI 2014 

  15. 15.Syed Mohammad Asad Hassan Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila and Hannu Tenhunen, ``RuRot: Run-time Rotatable-expandable Partitions for Efficient Mapping in CGRAs" SAMOS 2014 

  16. 16.B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, ``High Level Design Approach to Accelerate De Novo Genome Assembly using FPGAs", ASAP 2014 (Poster accepted but withdrawn)

  17. 17.Mansureh S, Kolin Paul M Balakrishnan``Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array" FCCM Toronto 2014

  18. 18.Syed Mohammad Asad Hassan Jafri, Kolin Paul, Masoud Daneshtalab, Ahmed Hemani, Juha Plosila,and Hannu Tenhunen``Morphable compression architecture for efficient configuration in CGRAs" FCCM Toronto 2014

  19. 19.Avval Gupta, Anjua Kansal, Kolin Paul and Sanjiva Prasad, ``mDROID - An Affordable Android based mHealth System", HEALTHINF 2014

  20. 20.Kolin Paul and Chinmaya Dash, ``A Reconfigurable  MultiProcessor Framework with A Fast Overlay Network", VLSI Design 2014

  21. 21.B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, ``Accelerating Genome Assembly using Hard  Embedded Blocks in FPGAs", VLSI Design 2014

  22. 22.Syed M. A. H. Jafri and Stanislaw J. Piestra and Ahmed Hemani and Kolin paul and Juha Plosila and Hannu Tenhunen, “Implementation and evaluation of configuration scrubbing on CGRAs: A case study” in International Symposium on System-on-Chip,Finland  2013

  23. 23.Ashutosh Jain, Anshuj Garg  and Kolin Paul, ``GAGM: Genome Assembly on GPU using  Mate pairs", 20th Annual International Conference on High Performance Computing (HiPC 2013), Bangalore 2013

  24. 24.Anshuj Garg, Ashutosh Jain and Kolin Paul, ``GGAKE: GPU based Genome Assembly using K-mer Extension", 15th IEEE International Conference on High Performance Computing and Communications (HPCC 2013), Zhangjiajie, China, November 13-15, 2013

  25. 25.Nasim Farhani,  Kolin Paul and Ahmed Hemani, ``Distributed Runtime Computation of Constraints for Multiple Inner Loops", EUROMICRO DSD 2013 Spain

  26. 26.Syed Mohammad Asad Hassan Jafri, Liang Guang, Ahmed Hemani, Juha Plosila, Kolin Paul and Hannu Tenhunen, ``Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs",EUROMICRO DSD 2013 Spain.

  27. 27.B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan and Dominique Lavenier, `` FAssem : FPGA based Acceleration of De Novo Genome Assembly" FCCM 2013 Washington USA.Mansureh S, Kolin Paul M Balakrishnan: Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs RAW 2013 Boston.

  28. 28.Nidhi, Kolin Paul, Ahmed Hemani and Anshul Kumar, High Performance 3D-FFT Implementation ISCAS 2013 China (accepted)

  29. 29.Kolin Paul, M Balakrishnan and Mansureh Shahraki Moghaddam: Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs, RAW 2013

  30. 30.Syed M. A. H. Jafri, Ozan Zeki Bag, Ahmed Hemani, Nasim Farahini, Juha Plosila and Hannu Tenhunen: Energy-aware coarse-grained Reconfigurable Architectures using Dynamically Reconfigurable Isolation Cells, ISQED 2013

  31. 31.Aarathi Prasad, Ronald A. Peterson, Shrirang Mare, Jacob Sorber, Kolin Paul, David Kotz: Provenance framework for mHealth. COMSNETS 2013: 1-6

  32. 32.B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan: Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. VLSI Design 2013: 92-97

  33. 33.Kolin Paul, Chinmaya Dash, Mansureh Shahraki Moghaddam: reMORPH: A Runtime Reconfigurable Architecture. DSD 2012: 26-33

  34. 34.Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen: Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes. DSD 2012: 242-249

  35. 35.Rajesh Kumar Pal, Kolin Paul, Sanjiva Prasad, ReKonf: A Recongurable Adaptive Many-Core Architecture, ISPA2012, Spain

  36. 36.Arun Parakh, M. Balakrishnan, Kolin Paul,Performance estimation for GPUs with cache", IEEE IPDPS PLC'12 Workshop", Shanghai, China 

  37. 37.Pei Liu, Kolin Paul, Ahmed Hemani, Improved Bioinformatics Processing Unit for Multiple Applications", RAW2012 Shanghai

  38. 38.Mohammad Asad, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen, Self-Adaptive NOC Power Management With Dual-Level Agents: Architecture and Implementation", SANES 2012, Italy.

  39. 39.Syed. M.A.H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen, "Compact Generic Intermediate representation (CGIR) to enable late binding in Coarse Grained Reconfigurable Architectures", FPT2011

  40. 40.Pei Liu, Fatemeh O. Ebrahim, Kolin Paul and Ahmed Hemani, "A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics", ReConFig 2011 (accepted)

  41. 41.Tapas Kumar Kundu, Kolin Paul, "Improving Android Performance and Energy Eficiency," pp.256-261, 2011 24th International Conference on VLSI Design, 2011

  42. 42.Pei Liu, Ahmed Hemani, Kolin Paul, "A Reconfigurable Processor for Phylogenetic Inference," pp.226-231, 2011 24th International Conference on VLSI Design, 2011

  43. 43.Syed. M.A.H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen, "Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures," pp.290-293, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops, 2011

  44. 44.Kolin Paul, Tapas Kumar Kundu: Android on Mobile Devices: An Energy Perspective. CIT 2010: 2421-2426

  45. 45.Sohan Lal, Kolin Paul and James Gomes, "Accelerating Metabolic Pathways Simulation using GPUs", ADPC 2010.

  46. 46.Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: A tiled programmable fabric using QCA. FPT 2010: 9-16

  47. 47.A High-Level Synthesis Flow for Custom Instruction Set Extensions for Application-Specific Processors. Nagaraju P, P Brisk, P Ienne, A Kumar and Kolin Paul, ASPDAC 2010.

  48. 48.Clocking-based Coplanar Wire Crossing Scheme for QCA. Rajeswari D, Kolin Paul, M Balakrishnan. VLSID 2010.

  49. 49.Kolin Paul and Tapas Kundu. Android on Mobile Devices: An Energy Perspective. V International Symposium on Advanced Topics on Embedded Systems and Applications. Bradford, UK, 29 June - 1 July, 2010

  50. 50.Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul, Dipendra Manocha. Smart Cane for the Visually Impaired: Design, Implementation and Field Tesing of an afiordable Obstacle Detection System. TRANSED 2010(Best Paper ).

  51. 51.Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul, Dipendra Manocha. User Triggered Bus Identification and Homing System: Making public transport accessible for the Visually Challenged. TRANSED 2010.

  52. 52.Reliable Context Detection for Improving Positioning Performance and Enhancing user Experience. M. Chowdhary, M. Chansarkar, M. Sharma, A. Kumar, Kolin Paul, M. Jain, C. Agarwal and G. Narula, ION GNSS 2009 Conference

  53. 53.Rajeswari D, Kolin Paul and M Balakrishnan. Clocking-based Coplanar Wire Crossing Scheme for QCA. International Workshop on Quantum-Dot Cellular Automata 2009

  54. 54.A Jain and P Gambhir and P Gupta and M Balakrishnan and Kolin Paul, "FPGA Accelerator for Protein Structure Prediction Algorithms" SPL 2009.

  55. 55.Nagaraju P, Anshul Kumar and Kolin Paul. A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. VLSID 2008. Hyderabad January, 2008.

  56. 56.Nagaraju P, Anshul Kumar and Kolin Paul. Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors VLSID 2008. Hyderabad January, 2008.

  57. 57.Neeraj Goel and Kolin Paul. Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture ADCOM 2007 Guwahati.

  58. 58.Kolin Paul Joel Porquet. Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. EUROMICRO Conference of Digital Systems Design 2007. August 27-31 2007. Lubeck Germany.

  59. 59.M. Balakrishnan, Kolin Paul, Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, Dipendra Manocha. PVM Rao, V Singh, V Goel, D Mukherjee. Cane Mounted Knee Above Obstacle Detection and Warning System for the Visually Impaired. 3rd  ASME/IEEE Conference on Mechatronics and Embedded Systems and Applications ASME-DETC 2007. September 4-7 2007, Las Vegas.

  60. 60.Nagaraju Pothineni Anshul Kumar Kolin Paul. Recurring Pattern Identi_cation and its Application to Instruction Set Extension. The 2007 International Conference on Computer Design (CDES'07) Las Vegas, Nevada, USA (June 25-28) 2007.

  61. 61.Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul, Dipendra Manocha. `Smart' Cane for the Visually Impaired:Technological Solutions for Detecting Waist-above Obstacles. TRANSED 2007 Montreal Canada June 2007

  62. 62.Nagaraju Pothineni Anshul Kumar Kolin Paul. Application Specific Datapath Extension with Distributed I/O Functional Units. VLSID 2007. Bangalore January, 2007.

  63. 63.Kolin Paul M Balakrishnan. Experiences of a Summer Workshop in Embedded Systems. Workshop on Embedded System Education, EMSOFT, South Korea . October, 2006.

  64. 64.Nilesh Padhariya, Kolin Paul and Dheeraj Bhardwaj. A FLOPS Based Model for Performance Analysis ICPP Workshops 2006.

  65. 65.Neeraj Goel and Kolin Paul. Fault Tolerant FPGA using Redundant Columns. Proc of VLSI Design and Test Symposium(VDAT 2006), Goa, India.. July, 2006.

  66. 66.Rahul Jain, Anindita Mukherjee and Kolin Paul. Defect-Aware Design Paradigm for Reconfigurable Architectures. IEEE Computer Society Annual IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006). April, 2006.

  67. 67.Kolin Paul and Sanjay Rajopadhye. Back Propagation Algorithm: Achieving 5 GOPS on the Virtex-E. Book Chapter in FPGA Implementations of Neural Networks By Amos R. Omondi; Jagath C. Rajapakse (Eds.). 0-387-28485-0 March, 2006.

  68. 68.H. Dhand, and N.Goel and M.Agarwal. H. Dhand, N.Goel, M.Agarwal and K.Paul, IIT Delhi Partial and Dynamic Reconfiguration in Xilinx FPGAs --A Quantitative Study. VDAT 2005. August, 2005.

  69. 69.Sanjay Rajopadhye and Kolin Paul . A 1.5-D Architecture for Back Propagation Training Engineering Of Reconfigurable Systems and Algorithms (ERSA'05) . June, 2005.

  70. 70.Clare Hugget and Koushik Maharatna and Kolin Paul. On the Implementation of 128-bit FFT/IFFT for High Performance WPAN. 2005 IEEE International Symposium 2005 IEEE International Symposium on Circuits and Systems. May, 2005.

  71. 71.Kolin Paul. An FPGA based Test Bed for Bio Inspired Computation. 12th Reconfigurable Architectures Workshop RAW 2005, Denver. April, 2005.

  72. 72.Kolin Paul and S Rajopadhye , A New Hardware/FPGA Implementation of the Back Propagation Algorithm" IEEE Annual Symposium on VLSI 2003

  73. 73.P. P. Chaudhuri, B. Sikdar, and Kolin Paul, Tutorial on Theory and Application of Cellular Automata CA for VLSI Design and Test", in VLSID'00 INDIA, January 2000.

  74. 74.Kolin Paul, D. R. Chowdhury, and P. P. Chaudhuri, Scalable Pipelined Micro-Architecture for Wavelet Transform", in Proc. of VLSID'00, INDIA, January 2000.

  75. 75.Kolin Paul and D. R. Chowdhury, Application of GF(2p) CA in Burst Error Correcting Codes", in Proc. of VLSID'00, INDIA, January 2000.

  76. 76. Kolin Paul, S. P. Chaudhuri, R. Ghosal, B. Sikdar, and D. R. Chowdhury, GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images", in Proc. of VLSID'00 INDIA, January 2000.

  77. 77.B. Sikdar, Kolin Paul, G. P. Biswas, C. Yang, V. Bopanna, S. Mukherjee, and P. P. Chaudhuri, Theory and Application of GF(2p ) Cellular Automata as On-Chip Test Pattern Generator", in Proc. of VLSI'00 INDIA, January 2000.

  78. 78. Kolin Paul, D. R. Chowdhury, and P. P. Chaudhuri, Cellular Automata Based Transform Coding for Image Compression", in Proc. of HiPC'99 INDIA, December 1999.

  79. 79.Kolin Paul, P. Dutta, D. R. Chowdhury, P. K. Nandi, and P. P. Chaudhuri, A VLSI Architecture for On-Line Image Decompression using GF(2p ) Cellular Automata", in Proc. Of VLSID'99 INDIA, January 1999.

  80. 80. Kolin Paul, A. Roy, P. K. Nandi, B. N. Roy, M. D. Purkhayastha, S. Chattopadhyay, and P. P. Chaudhuri, Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis", in Proc. of ATS'97 Singapore, December 1997.

  81. 81.Kolin Paul, D. R. Chowdhury, and P. P. Chaudhuri, A Parallel Architecture for Generation of Fractals", in Proc. of ADCOM'97 INDIA, January 1997.