The 2010 International Conference on Field-Programmable Technology (FPT'11)
New Delhi, India
12-14, December 2011
Preliminary Program
DATE	StartTime	EndTime	Title	Authors
12 Dec.
	08:50	09:00	Welcome
	09:00	10:00	Keynote Session 1.1	Chair:
			Field-Programmable Technology : The Next Ten Years and Beyond	Wayne Luk, Imperial College, London.
	10:00	11:20	Oral Session 1.2 - Achitectures and Platforms	Chair:
			Reconfigurable Acceleration and Dynamic Partial Self-Reconfiguration in General Purpose Computing	Ioannis Sourdis, Abhijit Nandy, Venkatasubramanian Viswanathan, Anthony Brandon, Dimitris Theodoropoulos and Georgi N. Gaydadjiev
			A Framework for FPGA Acceleration of Large Graph Problems: Graphlet Counting Case Study	Brahim Betkaoui, David Thomas, Wayne Luk and Natasa Przulj
			Cool Mega-Array: a highly energy efficient reconfigurable accelerator	Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki and Masaaki Kondo
			A Self-Healing Autonomous Neural Network Hardware for Trustworthy Biomedical Systems	Zhanpeng Jin and Allen Cheng
	11:20	12:00	Poster Session 1.3 with Tea/Coffee Break, see details below	Chair:
	12:00	13:20	Oral Session 1.4 - Applications	Chair:
			VLIW-SCORE: Beyond C for Sequential Control of SPICE FPGA Acceleration	Nachiket Kapre and Andre DeHon
			Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm	Kazuhiro Negi, Keisuke Dohi, Yuichiro Shibata and Kiyoshi Oguri
			Use of Embedded FPGA Resources in Implementations of 14 Round 2 SHA-3 Candidates	Rabia Shahid, Malik Umar Sharif, Marcin Rogawski and Kris Gaj
			Variable and Clause Elimination in SAT problems using an FPGA	Masayuki Suzuki and Tsutomu Maruyama
	13:20	14:20	Lunch
	14:20	16:20	Invited Industrial Session 1.5	Chair:
	16:20	16:50	Poster Session 1.3 with Tea/Coffee Break, see details below	Chair:
	16:50	18:10	Oral Session 1.6 - Analytical Modeling and Architecture	Chair:
			Constant Power Reconfigurable Computing	Adrien Le Masle, Gary C. T. Chow and Wayne Luk
			An Analytical Energy Model to accelerate FPGA Logic Architecture Investigation	Senthilkumar Thoravi Rajavel and Ali Akoglu
			Accelerated FPGA Architecture Design: Capabilities and Limitations of Analytical Model	Joydip Das and Steven J.E. Wilton
			A Scalable Memory Interface for Multicore Reconfigurable Computing Systems	Philip Garcia and Katherine Compton
	18:10	19:00	Break
	19:00	20:00	PhD Forum and Demo Session 1.7, see details below	Chair:
13 Dec.
	08:50	09:00	Welcome
	10:00	11:20	Oral Session 2.2 - CAD and design space exploration	Chair:
			A Unified Emulation/Simulation Environment for Reconfigurable System-on-Chip Development	Peter Crosthwaite, John Williams and Peter Sutton
			Exploring FPGA Technology Mapping For Fracturable LUT Minimization	David Dickin and Lesley Shannon
			Automating Formal Verification of Customized Soft-Processors	Kong Susanto and Wayne Luk
			Operational Mode Exploration for Reconfigurable Systems with Multiple Applications	Stefan Wildermann, Felix Reimann, Jürgen Teich and Zoran Salcic
	11:20	12:00	Poster Session 2.3 with Tea/Coffee Break, see details below	Chair:
	12:00	13:20	Oral Session 2.4 - Reliability and Security	Chair:
			Scrubbing-based SEU Mitigation Approach for Systems-on-Programmable-Chips	Aitzan Sari and Mihalis Psarakis
			Investigation of NBTI and PBTI induced aging in different LUT implementations	Saman Kiamehr, Abdulazim Amouri and Mehdi B.Tahoori
			A Side-Channel aware IP-Protection Scheme for FPGA-based Platforms	Marc Stöttinger, Thomas Feller and Sorin A. Huss
			Timing Speculation in FPGAs: Probabilistic Inference of Data Dependent Failure Rates	Sumanta Chaudhuri, Justin S. J. Wong and Peter Y. K. Cheung
	13:20	14:20	Lunch
	14:20	16:00	Oral Session 2.5 - Partial Reconfiguration	Chair:
			Reducing Power for Dynamically Reconfigurable Processor Array by Reducing Number of Reconfigurations	Masayuki Kimura, Kazuei Hironaka and Hideharu Amano
			Partially Reconfigurable System-on-Chips for Adaptive Fault Tolerance	Shaon Yousuf, Adam Jacobs and Ann Gordon-Ross
			ReSim: A Reusable Library for RTL Simulation of Dynamic Partial Reconfiguration	Lingkan Gong and Oliver Diessel
			Hardware-Accelerated Execution of Pi-Calculus Reconfiguration Schedules	Andre Seffrin and Sorin A. Huss
	16:00	16:10	Annoucement of FPT 2012
	16:10	16:40	Poster Session 2.3 with Tea/Coffee Break, see details below	Chair:
	16:40	17:40	Indian Special Session 2.6	Chair:
			Design & Development of Softcore Processor based Remote Terminal Units for Nuclear Reactors	Aditya Gour, A. Santhana Raj, N. Murali, S.A.V Satyamurty and R.P. Behera
			A Scalable Network Port Scan Detection System on FPGA	Tejasvi Anand, Yagnesh Waghela and Kuruvilla Varghese
			An adaptive-method for velocity estimation using time-to-digital converter	Mitesh Khadgi, Majid Koul and M Manivannan
			Design Methodology for Analog Circuit Designs using Proposed Field Programmable Basic Analog Building Blocks	Garima Kapur and CM Markan
	17:40	19:00	Break
	19:00	21:00	Banquet Dinner
14 Dec.
	09:00	10:00	Oral Session 3.1 - High Level Synthesis	Chair:
			Efficient Nested Loop Pipelining in High Level Synthesis using Polyhedral Bubble Insertion	Antoine Morvan, Steven Derrien and Patrice Quinton
			High Level Synthesis of Stereo Matching: Productivity, Performance, and Software Constraints	Kyle Rupnow, Yun Liang, Yinan Li, Dongbo Min, Minh Do and Deming Chen
			Performance and Productivity Evaluation of the HCE High Level Synthesis tool implementing Reverse Time Migration	Tassadaq Hussain, Miquel Pericas, Nacho Navarro and Eduard Ayguade
	10:00	11:00	Poster session 3.2 with Tea/Coffee Break	Chair:
	11:00	12:00	Design Contest Session 3.3	Chair:
	12:00	13:00	Keynote Session 3.4	Chair:
			Value of Rapid Prototyping in Building Complex Digital Systems	Arvind, Massachusetts Institute of Technology.
	13:00	14:20	Lunch
	14:20	16:20	Indian Field Programmable Technology Showcase 3.5	Chair:
	16:20	16:30	Ending Annoucement
			Poster, Demo, PhD Session Papers
12/12/2011			First Day Poster Session 1.3
			FPGA Implementation of Reconfigurable ADPLL Network for Distributed Clock Generation	Chuan SHAN, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Féruglio, Dimitri Galayko, Olivier Romain, Éric Colinet and Jérôme Juillard
			A Framework for Verifying Functional Correctness in Odin-II	Joseph Libby, Ashley Furrow, Paddy O'Brien and Kenneth Kent
			Floating-point Mixed-radix FFT Core Generation for FPGA and Comparison with GPU and CPU	Bo DUAN, Wendi WANG, Xingjian LI, Chunming ZHANG, Peiheng ZHANG and Ninghui SUN
			An analysis of ring oscillator PUF behavior on FPGAs	Susana Eiroa and Iluminada Baturone
			A Low Power Technology Mapping Method for Adaptive Logic Module	Wei Chen, Yuichi Nakamura, Xiaolin Zhang and Takeshi Yoshimura
			Hydrate: Hybrid Reconfigurable Architecture Expressions	ChiWai Yu, Fred Cox, Wayne Luk and Ray C.C. Cheung
			A Novel Architecture for a Secure Update of Cryptographic Engines on Trusted Platform Module	Sunil Malipatlolla, Thomas Feller, Abdulhadi Shoufan, Tolga Arul and Sorin A. Huss
			Interconnect-Topology Independent Mapping algorithm for a Coarse Grained Reconfigurable Architecture	Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita and S K Nandy
13/12/2011			Second Day Poster Session 2.3
			FPGA Power Consumption Measurements and Estimations Under Different Implementation Parameters	Dimitrios Meidanis, Konstantinos Georgopoulos and Ioannis Papaefstathiou
			Heterogeneous System Design Exploration for Energy Efficient Scientific Computing	Qiang Liu and Wayne Luk
			Design Methodology for FPGA Implementation of Lattice Piecewise-Affine Functions	Macarena Martinez-Rodriguez, Iluminada Baturone and Piedad Brox
			Accelerating On-Line Training of LS-SVM with Run-Time Reconfiguration	Shaojun Wang, Yu Peng, Guangquan Zhao and Xiyuan Peng
			High Speed Low Complexity FPGA-based FIR Filters Using Pipelined Adder Graphs	Martin Kumm and Peter Zipf
			Formulation-level Design Space Exploration for Partially Reconfigurable FPGAs	Rohit Kumar and Ann Gordon-Ross
			A Novel Online Hardware Task Scheduling and Placement Algorithm for 3D Partially Reconfigurable FPGAs	Thomas Marconi and Tulika Mitra
			Spiking Neural Network-based Auto-associative Memory Using FPGA Interconnect Delays	Chong Hau Ang, Andre van Schaik, Craig Jin and Philip Leong
			A Reconfigurable Macro-Pipelined Systolic Accelerator Architecture	Wenqi Bao, Jiang Jiang, Qing Sun and Yuzhuo Fu
14/12/2011			Third Day Poster Session 3.2
			Pipelined high precision beamforming delay calculator for ultrasound imaging	Zhanxiang Zhao, Xin Zhang and Xi Jin
			Compact Generic Intermediate representation (CGIR) to enable late binding in Coarse Grained Reconfigurable Architectures	Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila and Hannu Tenhunen
			Partial Reconfiguration Logic Synthesis by Temporal Slicing	Swamy Ponpandi and Akhilesh Tyagi
			Hardware Module Reuse and Runtime Assembly for Dynamic Management of Reconfigurable Resources	Abelardo Jara-Berrocal and Ann Gordon-Ross
			Efficient Key-Dependent Message Authentication in Reconfigurable Hardware	Jérémie Crenne, Pascal Cotret, Guy Gogniat and Jean-Philippe Diguet
			An FPGA-based Object Detector with Dynamic Workload Balancing	Chuan Cheng and Christos-Sawas Bouganis
			Sharing FPUs in Many-Soft-Cores	David Castells-Rufas, Eduard Fernandez-Alonso, Jaume Joven and Jordi Carrabina
			Runtime Stress-Aware Replica Placement on Reconfigurable Devices under Safety Constraints	Josef Angermeier, Daniel Ziener, Michael Glaß and Jürgen Teich
			Efficient Region Allocation for Adaptive Partial Reconfiguration	Kizheppatt Vipin and Suhaib A Fahmy
12/12/2011			First Day Phd Forum and Demo Session 1.7
			The Realtime Image Processing Demonstration with CMA-1 : An Ultra Low-power Reconfigurable Accelerator	Kazuei Hironaka, Nobuaki Ozaki and Hideharu Amano
			3D Implication Logic: Preliminary Results	Gina Adam
			Enabling High Level Design of Adaptive Systems with Partial Reconfiguration	Kizheppatt Vipin and Suhaib A Fahmy
			Analytical Models for Designing New FPGA Architectures and Devices	Joydip Das and Steve Wilton
			Architecture and Tools for Programmable QCA	Rajeswari Devadoss, Kolin Paul and M Balakrishnan