CS411N/719N: CAD of Digital Systems, Semester I, 2002-03
Due Date: October 28, 2002
Demo Date: October 29-30, 2002
- Write a non-pipelined cycle accurate sequential (process) VHDL description of one of the following
- Basic computer from Mano's book
- MIPS from Hennessey & Patterson's book
Your description should contain the following:
- Clearly indicate the parts which handle fetch, decode and execute.
- Enough instructions to implement a bubble sort algorithm
- Testbench containing the memory which is initialized with the bubble sort program for
sorting 16 numbers and 16 data values in proper location.
- Convert your design into a pipelined design with three processes, fetch, decode and execute.
Create an instruction buffer for handling variable execution time.