CS411N/719N: CAD of Digital Systems, Semester I, 2002-03

Assignment 2


Due    Date: October 28, 2002
Demo Date: October 29-30, 2002

Assignment Description

  1. Write a non-pipelined cycle accurate sequential (process) VHDL description of one of the following three processors:
    1. 8085
    2. Basic computer from Mano's book
    3. MIPS from Hennessey & Patterson's book

    Your description should contain the following:

    1. Clearly indicate the parts which handle fetch, decode and execute.
    2. Enough instructions to implement a bubble sort algorithm
    3. Testbench containing the memory which is initialized with the bubble sort program for sorting 16 numbers and 16 data values in proper location.

  2. Convert your design into a pipelined design with three processes, fetch, decode and execute. Create an instruction buffer for handling variable execution time.

Last Updated November 21, 2002 by Anup Gangwar