CS411N/719N: CAD of Digital Systems, Semester I, 2002-03
Due Date: September 30, 2002
Demo Date: October 1-2, 2002
In VHDL describe/design the following:
- 1-bit full adder (dataflow or structural).
- 1-digit BCD adder (structurally from above).
- Assume the two BCD inputs are coming serially (at the rate of 1 bit/clock cycle), design a FSM for
converthing this serial input to parallel 1-digit BCD.
- Structurally compose two instantiations of the serial-to-parallel BCD converter and one BCD adder.
Write a test bench and show addition of the following sequence of inputs "0010 0011 0110" and
"0010 0110 0001" (i.e. 236 and 261) digit by digit.