Anup Gangwar

URLs:

E-mail : anup AT cse.iitd.ernet.in
Home : http://www.cse.iitd.ernet.in
Group : http://embedded.cse.iitd.ernet.in
 

Courses Publications Resume Personal Links Quotes

Founder at VirtuQTM. For professional summary, check out my LinkedIn page. Do note that the resume linked to this page is not up-to-date.

Theses
  • A Methodology for Exploring Communication Architectures of Clustered VLIW Processors, [PDF]
    Anup Gangwar
    Ph.D. Thesis, Jul 2005, Department of Computer Science and Engineering, IIT Delhi, New Delhi, India.
    Advisors: Prof. M. Balakrishnan and Prof. Anshul Kumar

  • Multi-Processor Multi-Tasking Performance Data Measurement and Visualization,
    Anup Gangwar
    M.Tech (VDTT) Thesis, Dec 2000, Department of Computer Science and Engineering, IIT Delhi, New Delhi, India. (also published as Nat. Lab. Technical Note 2001/9, see below)
    Advisors: Dr. Ir. Jos van Eijndhoven, Prof. M. Balakrishnan and Prof. Anshul Kumar
Book Chapters
  • Customizing Embedded Processors for Specific Applications, [PDF]
    Anshul Kumar, M. Balakrishnan, Manoj Kumar Jain and Anup Gangwar,
    Recent Trends in Practice and Theory of Information Technology, Viva Books (ISBN: 8130901714), Jan 2005.
Papers
  • Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures [PDF]
    Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda and Anshul Kumar.
    International Journal of Parallel Programming (IJPP), Vol. 35, No. 6, Dec 2007.

  • Impact of Intercluster Communication Mechanisms on ILP in Clustered VLIW Architectures [PDF]
    Anup Gangwar, M. Balakrishnan and Anshul Kumar.
    ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 12, No. 1, Jan 2007.
    Receipient of ACM TODAES best paper award for the year 2006-2007. Photograph of awards ceremony during DAC-2007.

  • Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures [PDF]
    Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda and Anshul Kumar.
    IEEE/ACM Design Automation and Test in Europe (DATE05), Mar 2005, Munich, Germany.

  • SMPS: An FPGA-based Prototyping Environment for Multiprocessor Embedded Systems [PS.GZ]
    Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, and Subhashis Banerjee,
    IEEE/ACM Thirteenth International Symposium on Field Programmable Gate Arrays (FPGA-2005), Feb 2005, Monterey, USA. (Poster presentation)

  • Customizing Clustered VLIW Architectures with Focus on Interconnects and Functional Units
    Anup Gangwar, M. Balakrishnan and Anshul Kumar
    SIGDA Ph.D. Forum at 41st IEEE/ACM Design Automation Conference (DAC-41), Jun 2004, San Diego, USA.

  • Impact of Inter-cluster Communication Mechanisms on ILP in Clustered VLIW Architectures [PDF]
    Anup Gangwar, M. Balakrishnan and Anshul Kumar.
    2nd Workshop on Application Specific Processors (WASP-2), in conjuction with 36th IEEE/ACM Annual International Symposium on Microarchitecture (MICRO-36), Dec 2003, San Diego, USA.

  • SoC Synthesis With Automatic Interface Generation [PDF]
    Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant K. Dwivedi, M. Balakrishnan and Anshul Kumar,
    16th IEEE/ACM International Conference on VLSI Design (VLSI-2003), Jan 2003, New Delhi, India.

  • A Trimaran Based Framework for Exploring Design Space of VLIW ASIPs With Coarse Grain Functional Units [PDF]
    Bhuvan Middha, Varun Raj, Anup Gangwar, Anshul Kumar, M. Balakrishnan and Paole Ienne,
    15th IEEE/ACM International Symposium on System Synthesis (ISSS'02), Oct 2002, Kyoto, Japan.

  • Multi-Processor Multi-Tasking Performance Data Measurement and Visualization [PS.GZ] (public version only)
    Anup Gangwar, Jos T. J. van Eijndhoven, M. Balakrishnan and Anshul Kumar,
    Nat. Lab. Technical Note 2001/9, Jan 2001, PRLE, Eindhoven, The Netherlands.
Seminars
  • Ph.D. in Computer Science: Why, How and From Where [PDF],
    Departmental Seminar Series, Apr 2008, Department of Computer Science and Engineering, IIT Delhi, India.

  • A Tutorial on VHDL Synthesis, Place and Route for FPGA and ASIC Technologies [PDF],
    Embedded Systems Group Seminar Series, Oct 2004, Department of Computer Science and Engineering, IIT Delhi, India.

  • Implementation Characterstics of Interconnect Mechanisms in Clustered VLIW Architectures [PDF],
    Ph.D. Thursday Seminar Series, Aug 2004, Department of Computer Science and Engineering, IIT Delhi, India.

  • Inter-cluster Communication in Clustered VLIW Architectures,
    Inter Research Institute Student Seminars (IRISS-2004), Mar 2004, Department of Computer Science and Engineering, IIT Bombay, India.

  • Code Scheduling Techniques for VLIW Architectures and Their Applicability to Clustered Architectures [PDF],
    Ph.D. Thursday Seminar Series, Mar 2004, Department of Computer Science and Engineering, IIT Delhi, India.

  • Evaluating Inter-cluster Communication in Clustered VLIW Architectures [PDF],
    Ph.D. Thursday Seminar Series, Sep 2003, Department of Computer Science and Engineering, IIT Delhi, India.

  • Synthesis and Testing of LEON Soft Processor Core Over ADM-XRC [PPT],
    Embedded Systems Group Seminar Series, Aug 2002, Department of Computer Science and Engineering, IIT Delhi, India.

  • Ph.D. Research Plan Presentation [PPT],
    SRC Presentation, Jun 2002, Department of Computer Science and Engineering, IIT Delhi, India.

  • Framework for studying effect of VLIW encoding and decoding schemes [PPT],
    Minor-project Presentation, Nov 2001, Department of Computer Science and Engineering, IIT Delhi, India.

  • A Brief Introduction to The Trimaran Compiler Research Infrastructure [ZIPPED PPT],
    Embedded Systems Group Seminar Series, Mar 2001, Department of Computer Science and Engineering, IIT Delhi, India.

  • Instruction Level Parallelism for Low-Power Embedded Processors (Ph.D. thesis of Jean Michel-Puiatti, EPFL) [ZIPPED PPT],
    Embedded Systems Group Seminar Series, Jan 2001, Department of Computer Science and Engineering, IIT Delhi, India.

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Last Updated Jun 21, 2011 © Anup Gangwar, Department of CSE, IIT Delhi
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