System-on-Chip Interconnects [PDF]
Anup Gangwar, Ant Harris and David J. Greaves
Modern SoC Design, Arm Education Media (ISBN:978-1-911531-36-4), Aug 2021.

Customizing Embedded Processors for Specific Applications [PDF]
Anshul Kumar, M. Balakrishnan, Manoj Kumar Jain and Anup Gangwar,
Recent Trends in Practice and Theory of Information Technology, Viva Books (ISBN: 8130901714), Jan 2005.

A configurable Network-on-Chip with novel automated tooling scaling to 100s of interfaces
Anup Gangwar and Premkumar Shivakumar
Arm Developer Summit (Arm DevSummit), Oct, 2021.

Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip
Anup Gangwar, Ravishankar Sreedharan, Ambica Prasad, Nitin Kumar Agarwal and Sri Harsha Gade
IEEE/ACM Design Automation Conference (DAC), 2021.

An Automated Traffic Generation Framework for Performance Evaluation of Networks-on-Chip for Real World Use Cases [IEEEXplore]
Sri Harsha Gade, Anup Gangwar, Ambica Prasad, Nitin Kumar Agarwal, Ravishankar Sreedharan
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2021. (Poster presentation)

Automated Synthesis of Custom Networks-on-Chip for Real World Applications [IEEEXplore]
Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad, Sri Harsha Gade, Zheng Xu
IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020.

Traffic Driven Automated Synthesis of Network-on-Chip from Physically Aware Behavioral Specification [IEEEXplore]
Anup Gangwar, Zheng Xu, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019.

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures [PDF]
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda and Anshul Kumar.
International Journal of Parallel Programming (IJPP), Vol. 35, No. 6, Dec 2007.

Impact of Intercluster Communication Mechanisms on ILP in Clustered VLIW Architectures [PDF]
Anup Gangwar, M. Balakrishnan and Anshul Kumar.
ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 12, No. 1, Jan 2007.
Receipient of ACM TODAES best paper award for the year 2006-2007. Photograph of awards ceremony during DAC-2007.

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures [PDF]
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda and Anshul Kumar.
IEEE/ACM Design Automation and Test in Europe (DATE), Mar 2005, Munich, Germany.

SMPS: An FPGA-based Prototyping Environment for Multiprocessor Embedded Systems [PS.GZ]
Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, and Subhashis Banerjee,
IEEE/ACM Thirteenth International Symposium on Field Programmable Gate Arrays (FPGA), Feb 2005, Monterey, USA. (Poster presentation)

Customizing Clustered VLIW Architectures with Focus on Interconnects and Functional Units
Anup Gangwar, M. Balakrishnan and Anshul Kumar
SIGDA Ph.D. Forum at 41^st IEEE/ACM Design Automation Conference (DAC), Jun 2004, San Diego, USA.

Impact of Inter-cluster Communication Mechanisms on ILP in Clustered VLIW Architectures [PDF]
Anup Gangwar, M. Balakrishnan and Anshul Kumar.
2^nd Workshop on Application Specific Processors (WASP-2), in conjuction with 36^th IEEE/ACM Annual International Symposium on Microarchitecture (MICRO), Dec 2003, San Diego, USA.

SoC Synthesis With Automatic Interface Generation [PDF]
Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant K. Dwivedi, M. Balakrishnan and Anshul Kumar,
16^th IEEE/ACM International Conference on VLSI Design (VLSI-Design), Jan 2003, New Delhi, India.

A Trimaran Based Framework for Exploring Design Space of VLIW ASIPs With Coarse Grain Functional Units [PDF]
Bhuvan Middha, Varun Raj, Anup Gangwar, Anshul Kumar, M. Balakrishnan and Paole Ienne,
15^th IEEE/ACM International Symposium on System Synthesis (ISSS), Oct 2002, Kyoto, Japan.

Multi-Processor Multi-Tasking Performance Data Measurement and Visualization [PS.GZ] (public version only)
Anup Gangwar, Jos T. J. van Eijndhoven, M. Balakrishnan and Anshul Kumar,
Nat. Lab. Technical Note 2001/9, Jan 2001, PRLE, Eindhoven, The Netherlands.

A Methodology for Exploring Communication Architectures of Clustered VLIW Processors, [PDF]
Anup Gangwar
Ph.D. Thesis, Jul 2005, Department of Computer Science and Engineering, IIT Delhi, New Delhi, India.
Advisors: Prof. M. Balakrishnan and Prof. Anshul Kumar

Multi-Processor Multi-Tasking Performance Data Measurement and Visualization,
Anup Gangwar
M.Tech (VDTT) Thesis, Dec 2000, Department of Computer Science and Engineering, IIT Delhi, New Delhi, India. (also published as Nat. Lab. Technical Note 2001/9, see below)
Advisors: Dr. Ir. Jos van Eijndhoven, Prof. M. Balakrishnan and Prof. Anshul Kumar