Under this research project, we wish to explore application specific, heterogeneous, ASIP (VLIW and RISC) based multiprocessor System on Chip. The basic idea is to develop an integrated framework for synthesis of embedded systems built around such multiprocessors where both system and subsystem-level design-spaces can be efficiently explored.

Today Embedded Systems on a Chip (SoCs) can be found in a large variety of applications like image processing, computer vision, networking, wireless communication etc. Typically these applications demand real time processing and high throughput. Many of these applications, specially in the domain of image processing and computer vision, also offer good amount of functional and data parallelism. Multiprocessors, fine tuned for these applications become one of the obvious choices because of the computing power they offer by exploiting the parallelism effectively. Most of the present embedded systems do not use multiprocessors. They essentially comprise of a processor and some hardware built around it. The software is used for achieving fast turn around times while the hardware is used to speed up critical portions of the system. On the other hand shared memory multiprocessors are very popular in the server segment. The reasons, why these architectures have not been used in embedded systems, are large latency of off-chip processor communication and high cost. Now as the technology is slowly moving towards nanometer era, it is possible to fabricate billions of transistors on a single chip. This will also dramatically reduce the communication cost among processors in a multiprocessor architecture when implemented on a single chip. The main motivating factors behind investigating a synthesis methodology for multiprocessor systems on a chip, are the great amount of parallelism present in several applications which demand real time processing and technology trends. Another aspect which motivates the need for multiprocessor SoCs is control. While in a single chip SoC with hardware accelerators the single processor is expected to coordinate the various accelerators, in a multiprocessor SoC this task can be offloaded to one processor leaving others free to participate in computation. In fact, SoCs with two processors, one for control and one for Digital Signal Processing have already become common.

Architecture customization leads to design solutions which are cheaper cost-wise as well as satisfy the constraints on performance and power consumption tightly. The General Purpose Computing domain doesn't offer much opportunity for architecture customization as it is not known in advance which application will run on the target architecture. However, in embedded systems the application is known in advance and as a consequence it is possible to analyze the application rigorously and fine tune the architecture. Thus Application Specific Instruction Processors (ASIPs) are important components of SoCs. As an example, consider a image processing application, where the image itself is represented as an array of bytes. This offers a possible customization opportunity wherein the datapath is itself designed keeping the above fact in mind. This decreases the word size of the ALU, bus, registers etc. all leading to a design solution which is much cheaper. Another example of customization opportunity is the memory access pattern of some applications. If, say the application accesses the memory elements in FIFO order, then the memory architecture itself can be fine tuned alongwith the address generation unit. At the system level, the inter-component communications network can be customized, specific tasks can be offloaded to dedicated processors, the number and types of processors can be appropriately chosen etc.

Under the Srijan project we are trying to investigate all these issues and develop a methodology for automatic synthesis of such systems. The word Srijan itself is taken from Sanskrit, its closest translation in English is Synthesis.