Accurate Energy Modelling of the Cache Sub-System
Sponsor Freescale Semiconductor

Design and Development of a Digital Processor for SHWS
Sponsor DRDO

Low power design methodology for embedded processor based systems
Sponsor Ministry for Human Resources Development

Development of a Platform for reconfigurable Computing
Sponsor Planning IIT Delhi

A Framework for CoDesign Solutions for High-performance Scientific Applications
Sponsor European Aeronautic Defence and Space Company

Reconfigurable Computing High Level Specification, Modeling and Synthesis of Run-time Reconfigurable Systems
Sponsor European Aeronautic Defence and Space Company

Component and System Level Design Techniques for Mobile Platform
Sponsor Intel Technology India

Task Migration in Multi-core Systems: Power Modelling and Optimisation
Sponsor Intel Technology India

The "Smart Cane" Project
Sponsor Media Lab Asia

Fast data dump for procesor debug
Sponsor Intel Technology India Pvt. Ltd

A Framework for System-level Power Estimation
Sponsor Thrust Area - IIT Delhi
Duration September 2004 to September 2006

Exploration of On-chip Memory Architectures in Embedded Systems
Sponsor Dept. of Science and Technology
Duration July 2003 to July 2006

A Methodology for Synthesis of ASIP Based Multiprocesor SoCs
Sponsor Naval Research Board
Duration November 2002 to March 2007

Methodology for heterogeneous implementation of Real-time embedded systems for Vision/Image processing.
Sponsor Naval Research Board
Duration March, 1998 to July, 2002

A Methodology for Automated Synthesis of RISC-ASIPs
Sponsor Naval Research Board
Duration July 2000 - July 2003