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Vector Datapath extentions in OR1200 processorThe execution speeds in a processor can be enhanced by providing a vector data-path in parallel to the existing scalar pipeline. Vector Processors have been at the heart of super-computers since their start and have the capability of tremendously improving the performance of processors. But typical vector processors have an associated problem that they require high memory bandwidth. In spite of such disadvantages, vector architectures involve some inherent advantages like low code complexity and higher performance. In order to employ the advantages offered by vector processors, the focus of current research is on implementing the vector architecture over the scalar memory bandwidth itself. A lot of research is going on in increasing the functionality of open source soft processor, OR1200. In this project we present our own architecture for implementing a vector data-path in an OR1200 processor by employing the existing memory bandwidth.Project page and download Automatic Wrapper Generation of Custom IPs for Platform FPGAsThis project involves the design of an Automatic Wrapper Generation wizard which can automatically create the interface of a user defined peripheral for the AMBA APB bus in the Leon architecture. Using this wizard, the user can input the information about the Custom IP like the name, starting address and the size of the address space of the IP into the corresponding fields and in return the wizard will generate the wrapper template HDL files. In addition to the HDL files the wizard also generates the driver template files to run an application using that IP. The user can just instantiate its Custom IP into the wrapper templates and does a simple port mapping. Presently a few services have been implemented into the wizard which can be extended further to include some more servicesProject page and download |