- Texture Filter Memory - A Power-efficient and Scalable Texture Memory Architecture for Mobile Graphics Processors
B.V.N.Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G.S. Vishweswaran
To Appear in International Conference on Computer Aided Design (ICCAD),
Saltlake, USA, Nov 2008
PDF[92k]
- A Framework for Energy Consumption Based Design Space Exploration for Wireless Sensor Nodes
Sonali Chouhan, M. Balakrishnan, Ranjan Bose
In International Symposium on Low Power Electronics and Design (ISLPED),
Bangalore, India, Aug 2008.
PDF[181k]
- Unified Modeling Abstraction for Fast Simulation and Emulation
Gummidipudi Krishnaiah, Preeti Ranjan Panda, Ashok Jagannathan, Sreenivas Subramoney, Anshul Kumar
In 3rd Workshop on Architectural Research Prototyping (WARP-2008) ,
Held in conjuncton with ISCA 35, Beijing, China, June 2008
PDF[79k]
- REWIRED - Register Write Inhibition by Resource Dedication
Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda
In 13th Asia and South Pacific Design Automation Conference ,
Seoul, Korea, Jan 2008
PDF[92k]
- Exhaustive Enumeration of Custom Instructions for Extensible Processors
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
In Int Conference in VLSI Design and Embedded System (VLSI
2008), Hyderabad, India, Jan 2008
PDF[155k]
- A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
In Int Conference in VLSI Design and Embedded System (VLSI
2008), Hyderabad, India, Jan 2008
PDF[214k]
- Evaluation of Bus Based Interconnect
Mechanisms in Clustered VLIW Architectures
Anup Gangwar, M Balakrishnan, Anshul Kumar and Preeti Ranjan Panda
International Journal of Parallel Programming (IJPP),
Springer Netherlands, Vol 35, No 6, December 2007
PDF[444k]
- Cane Mounted Knee-above Obstacle
Detection and Warning System for the visually impaired
M Balakrishnan, Kolin Paul, Ankush Garg, Rohan Paul, Dheeraj
Mehra, Vaibhav Singh, P.V.M. Rao, Vishwas Goel, Debraj Chatterjee,
Dipendra Manocha,
3rd ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications
(MESA 2007), Las Vegas, Nevada, USA, September 2007
PDF[605K]
- A Behavioral Synthesis Approach for
Distributed Memory FPGA Architectures
Ashutosh Pal and M Balakrishnan
17th International Conference on Field Programmable
Logic and Applications (FPL 2007), Amsterdam, Netherlands, August 2007
PDF[1072K]
- Silicon Compaction/Defragmentation for
Partial Runtime Reconfiguration
Kolin Paul and Joel Porquet
10th Euromicro conference on Digital System
Designa (DSD 2007), Lubeck, Germany, August 2007
PDF[548K]
- Energy Based Design Space Exploration
of Multiprocessor VLIW Architectures
Manoj Gupta, Mayank Gupta, Neeraj Goel, M.Balakrishnan,
10th Euromicro conference on Digital System
Design (DSD 2007), Lübeck, Germany, August 2007
PDF[228K]
- Recurring Pattern Identification and
its Application to Instruction Set Extension
Nagaraju Pothineni, Anshul Kumar, and Kolin Paul,
International Conference on Computer Design
(CDES 2007), Las Vegas, Nevada, USA, June 2007
PDF[512K]
- Smart Cane for the Visually Impaired:
Technologocal Solutions for Detecting Knee
Above Obstacles and Accessing Public Buses
Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra,
M. Balakrishnan, Kolin Pauk, Dipendra Manocha
11th International Conference on Mobility and Transport for Elderly and Disabled
Persons (TRANSED 2007), Montreal, Canada, June 2007
PDF[282k]
- An Efficient Pipelined VLSI Architecture
for Lifting-Based 2D-Discrete Wavelet Transform
Rahul Jain and Preeti Ranjan Panda
In International Symposium on Circuits and Systems (ISCAS
2007), New Orleans, May 2007
PDF[156K]
- The Impact of Loop Unrolling on Controller Delay in High Level Synthesis
Srikanth Kurra, Neeraj K Singh and Preeti Ranjan Panda
In Design Automation and Test in Europe(DATE) 2007, Acropolis, Nice, France April 2007
PDF [200k]
- Impact of intercluster communication
mechanisms on ILP in clustered VLIW architectures,
Anup Gangwar, M Balakrishnan and Anshul Kumar
ACM Transactions on Design Automation of Electronic
Systems (TODAES), Vol 12, No. 1, Jan 2007.
PDF [596k]
2007 ACM TODAES best paper award
- Application Specific Datapath
Extension with Distributed
I/O Functional Units,
Nagaraju Pothineni, Anshul Kumar and Kolin Paul
In Int Conference in VLSI Design and Embedded System(VLSI
2007), Bangalore, India,
January 2007
PDF [108k]
- Customization of Register File Banking
Architecture for Low Power,
Rakesh Nalluri, Rohan Garg and Preeti Ranjan Panda
In Int Conference in VLSI Design and Embedded System(VLSI
2007) Bangalore, India, Jan 2007.
PDF [200k]
- Memory Architecture Exploration for
Power-Efficient 2D-Discrete Wavelet Transform,
Rahul Jain and Preeti Ranjan Panda
In Int Conference in VLSI Design and Embedded System(VLSI
2007) Bangalore, India, Jan 2007.
PDF [123k]
- Power Reduction in VLIW Processor with
Compiler Driven
Bypass Network,
Neeraj Goel, Anshul Kumar and Preeti Ranjan Panda
In Int Conference in VLSI Design and Embedded System(VLSI
2007) Bangalore, India, Jan 2007.
PDF [76k]
- New Approach to Architectural
Synthesis: Incorporating QoS
Constraint
Harsh Dhand, Basant Kumar Dwivedi and M Balakrishnan
In Proc of 6th ACM and IEEE conference on Embedded
Software (EMSOFT- 2006), Seoul, South Korea, October 2006
[PDF] [248k]
- Energy efficient application specific
banked register files
Rakesh Nalluri and Preeti Ranjan Panda
In 10th IEEE VLSI Design And Test Symposium(VDAT 2006),
Goa, India, August 2006
[PDF] [236k]
- A power efficient architecture for 2-D
Discrete Wavelet Transform
Rahul Jain and Preeti Ranjan Panda
In 10th IEEE VLSI Design And Test Symposium(VDAT 2006),
Goa, India, August 2006
[PDF] [248k]
- Fault Tolrents FPGA using Redundant
Columns
Neeraj Goel and Kolin Paul
In 10th IEEE VLSI Design And Test Symposium(VDAT 2006),
Goa, India, August 2006
PDF [228k]
- Rapid Estimation of Control Delay from
High-Level
Specifications
Gagan Raj Gupta, Madhur Gupta and Preeti Ranjan Panda
43rd Design Automation Conference (DAC-2006), San
Francisco, USA, July 2006.
PDF [856k]
- Rapid Resource-Constrained Hardware
Performance Estimation
Basant K. Dwivedi, Arun Kejariwal, M. Balakrishnan and Anshul Kumar
International Workshop on Rapid System Prototyping (RSP06),
Chania, Crete, Greece, June 2006.
PDF [184k]
- Defect-Aware Design Paradigm for
Reconfigurable
Architectures.
Rahul Jain, Anindita Mukherjee and Kolin Paul
In Proc of IEEE Computer Society Annual Symposium on VLSI
(ISVLSI 2006),
Munich, Germany, April 2006
PDF [240k]
- Abridged Addressing: A Low Power
Memory Addressing Strategy
Preeti Ranjan Panda
11th Asia and South Pacific Design Automation Conference
(ASPDAC 2006),
Yokohama, Japan, January 2006
PDF [220k]
-
Factoring Large Numbers Using FPGAs
Akhilesh Chaudhary, Gaurav Gupta and M Balakrishnan
In Proc of VLSI Design And Test Symposium(VDAT 2005),
Banglore, India, August 2005
DOC [112k]
-
A Technique for Predicting the Effect of Data Cache
Associativity
Viresh Kumar and Preeti Ranjan Panda
In Proc of VLSI Design And Test Symposium(VDAT 2005),
Banglore, India, August 2005
PDF [128k]
-
Partial and Dynamic
Reconfiguration in Xilinx FPGAs - A Quantitative Study
Harsh Dhand, Neeraj Goel, Mukesh C Aggarwal, Kolin Paul
In Proc of VLSI Design And Test Symposium(VDAT 2005),
Banglore, India, August 2005
DOC [148k]
-
RPNG: A Tool for Random Process Network Generation
Basant Kumar Dwivedi, Harsh Dhand, M.Balakrishnan and Anshul Kumar
In Proc of Asia and South Pacific International Conference
in Embedded SoCs (ASPICES-2005) , Banglore, India, July 2005
PDF [108k]
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Evaluation of Bus Based Interconnect Mechanisms in
Clustered VLIW Architectures,
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda and Anshul Kumar
IEEE/ACM Design Automation and Test in Europe (DATE05),
Munich, Germany, March 2005.
PDF [191k]
-
SMPS: An FPGA-based Prototyping Environment for
Multiprocessor Embedded Systems,
Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M.
Balakrishnan, and Subhashis Banerjee
IEEE/ACM Thirteenth International Symposium on Field
Programmable Gate Arrays (FPGA-2005)
, Monterey, USA, February 2005
PS.GZ [640k]
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Integrated On-chip Storage Evaluation in ASIP Synthesis ,
Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar
Proc. 18th International Conference on VLSI Design
(VLSI-2005), Kolkata, India,
January 2005.
PDF [108k]
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ADOPT - An Approach to Activity Based Delay Optimization,
Gaurav Arora, Abhishek Sharma, M. Balakrishnan and D. Nagchoudhuri
Proc. 18th International Conference on VLSI Design
(VLSI-2005), Kolkata, India,
January 2005.
PDF [160k]
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Battery Model for Embedded System,
Gaurav Singhal, Venkat Rao, Anshul Kumar and Nicolas Navet,
Proc. 18th International Conference on VLSI Design
(VLSI-2005), Kolkata, India, January 2005.
PDF[180k]
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Customizing Embedded Processors for Specific Applications,
Anshul Kumar, M. Balakrishnan, Manoj Kumar Jain and Anup Gangwar,
Recent Trends in Practice and Theory of Information
Technology,
Proc. of NRB Seminar, 10-11 January 2005, NPOL, Cochin, pp. 261-284
PDF [408k]
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Automatically Customizing VLIW Architectures with Coarse
Grained Application-Specific Functional Units,
Diviya Jain, Anshul Kumar, Laura Pozzi, and Paolo Ienne,
Proc. 8th International Workshop on Software and
Compilers for Embedded Systems (SCOPES-2004), Amsterdam,The
Netherlands, September 2004.
PS(gzipped)
[64k]
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Automatic Synthesis of System on Chip Multiprocessor
Architectures for Process Networks,
Basant Kumar Dwivedi, Anshul Kumar and M. Balakrishnan,
Proc. International Conference on Hardware/Software
Codesign and System Synthesis (CODES+ISSS 2004), Stockholm, Sweden,
September 2004.
PS(gzipped) [60k]
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An Efficient Technique for Exploring Register File Size in
ASIP Design,
Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar,
IEEE Transaction on CAD (TCAD), Volume:23, Issue:12,
December 2004, page1693-1699.
PDF[88k]
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Customizing Clustered VLIW Architectures with Focus on
Interconnects and Functional Units,
Anup Gangwar, M. Balakrishnan and Anshul Kumar,
7th SIGDA Ph.D. Forum at 41st Design Automation Conference
(DAC-41),
San Diego, USA, June 2004.
PS [175k]
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Synthesis of Application Specific Multiprocessor
Architectures for Process Networks,
Basant Kumar Dwivedi, Anshul Kumar and M. Balakrishnan,
Proc. 17th International Conference on VLSI Design
(VLSI-2004), Mumbai, India, January 2004.
PS(gzipped)[36k]
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Real Time Dynamic Voltage Scaling for Embedded Systems,
Venkat Rao, Gaurav Singhal, and Anshul Kumar,
Proc. 17th International Conference on VLSI Design
(VLSI-2004), Mumbai, India, January 2004.
PS(gzipped)[36k]
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Performance Analysis of Inter Cluster Communication
Methods in VLIW Architectures,
Saurabh Saluja and Anshul Kumar,
Proc. 17th International Conference on VLSI Design
(VLSI-2004), Mumbai, India, January 2004.
PDF[242k]
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Impact of Inter-cluster Communication Mechanisms on ILP in
Clustered VLIW Architectures,
Anup Gangwar, M. Balakrishnan and Anshul Kumar,
Workshop on Application Specific Processors (WASP-2, in
conjuction with MICRO-36), San Diego, USA, Dec. 2003.
PDF[234k]
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Exploring Storage Organization in ASIP Synthesis,
Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar,
Euromicro Symposium on Digital System Design (Euro-DSD
2003), Belek Near Antalya, Turkey, September 2003.
PS(gzipped)[100k]
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Hybrid Multi-FPGA Board Evaluation by Permitting Limited
Multi-Hop Routing.
Sushil Chandra Jain, Anshul Kumar, Shashi Kumar,
Design Automation of Embedded Systems, Kluwer Academic
Publishers, No. 8, 2003, pp 309-326.
-
A Complexity Effective Communication Model for Behavioral
Modeling of Signal Processing Applications,
Satya Kiran M. N. V., Jayram M. N., Pradeep Rao and S. K. Nandy,
40th Design Automation Conference (DAC-03), Anaheim,
California, June 200
3.
PS(gzipped)[40k]
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SoC Synthesis With Automatic Interface Generation,
Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant K. Dwivedi, M.
Balakrishnan and Anshul Kumar
16th International Conference on VLSI Design (VLSI-2003),
New Delhi, India, January 2003, pp. 585-590
PS(gzipped)[176k]
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Design of a 2D DCT/IDCT Application Specific VLIW
Processor Supporting Scaled and Sub-Sampled Blocks,
Rohini Krishnan, O. P. Gangwal, Anshul Kumar and Jos Van Eijndhoven,
16th International Conference on VLSI Design (VLSI-2003),
New Delhi, India, January 2003.
PDF(gzipped)[123k]
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Exploring the Number of Register Windows in ASIP Synthsis,
Vishal P. Bhatt, M. Balakrishnan and Anshul Kumar,
VLSI Design/ASPDAC 2002, Bangalore, India, pp.
233-238, Jan. 2002.
PS(gzipped)[102k]
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A New Divide and Conquer Method for Achieving High-speed
Division in Hardware,
K. N. Murali Mohan, Rohini Krishnan, Anshul Kumar and M. Balakrishnan,
VLSI Design/ASPDAC 2002, Bangalore, India, January
2002, pp. 535-540
PS(gzipped)[253k]
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Multi-hop Routing of Multi-terminal Nets for Evaluation of
Hybrid Multi-FPGA Boards,
Sushil Chandra Jain, Anshul Kumar and Shashi Kumar,
IEEE International Conference on Field-Programmable
Technology (FPT-2002), Hong Kong, China, December 2002.
PS(gzipped)[167k]
-
An Efficient Technique for Exploring Register File Size in
ASIP Synthesis,
Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar,
International Conference on Compilers, Architectures and
Synthesis forEmbedded Systems (CASES 2002), Grenoble, France,
October 2002, pp. 252-261.
PS(gzipped)[87k]
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A New Performance Evaluation Approach for System Level
Design Space Exploration,
C. P. Joshi, Anshul Kumar and M. Balakrishnan,
15th International Symposium on ystem Synthesis (ISSS-2002),
Kyoto, Japan, October 2002, pp. 180-185.
PS(gzipped)[167k]
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A Trimaran Based Framework for Exploring Design Space of
VLIW ASIPs With Coarse Grain Functional Units,
Bhuvan Middha, Varun Raj, Anup Gangwar, M. Balakrishnan, Anshul Kumar
and Paolo Ienne,
15th International Symposium on ystem Synthesis (ISSS-2002),
Kyoto, Japan, October 2002, pp. 2-7.
PDF(gzipped)[91k]
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Reducing Energy Consumption by Dynamic Copying of
Instructions onto Onchip Memory,
Stefan Steinke, Nils Grunwald, Lars Wehmeyer, Rajeshwari Banakar, M.
Balakrishnan and Peter Marwedel,
15th International Symposium on ystem Synthesis (ISSS-2002),
Kyoto, Japan, October 2002, pp. 213-218.
PS(gzipped)[45k]
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Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop
Routing,
Sushil Chandra Jain, Anshul Kumar and Shashi Kumar,
13th IEEE International Workshop on Rapid System
Prototyping (RSP-2002), Darmstadt, Germany.
PS(gzipped)[103k]
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Scratchpad Memory: A Design Alternative for Cache On-Chip
Memory in Embedded Systems,
Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan and
Peter Marwedel,
10th International Symposium on Hardware/Software Codesign
(CODES-2002), Colorado, USA, pp. 73-78.
PS(gzipped)[56k]
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Synthesizing a Long Latency Unit Within VLIW Processor,
Ram Lakhan Gupta, Anshul Kumar, A. Van Der Werf and G. Natalio Busa,
International Conference on VLSI Design (VLSI-2001),
Bangalore, India, pp. 460-465, January 2001.
-
ASIP Design Methodologies : Survey and Issues,
Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar,
14th International Conference on VLSI Design (VLSI-2001),
Bangalore, India, pp. 76-81, January 2001.
PS(gzipped)[31k]
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Integrating Communication Cost Estimation in Embedded
Systems Design : A PCI case Study,
Anupam Rastogi, M. Balakrishnan and Anshul Kumar,
14th International Conference on VLSI Design (VLSI-2001),
Bangalore, India, pp. 23-28, January 2001.
PS(gzipped)[108k]
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Analysis of the Influence of Register File Size on Energy
Consumption, Code Size and Execution Time,
Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M.
Balakrishnan,
IEEE Transaction on CAD, vol. 20, no. 11, pp.
1329-1337, Nov. 2001
PS(gzipped)[359k]
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Using an Energy Aware Compiler Framework to Evaluate
Changes in Register File Size Towards ASIP-Design,
Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M.
Balakrishnan,
Fifth International Workshop on Software and Compilers for
Embedded Systems (SCOPES-2001), St. Goar, Germany, March 2001.
PS(gzipped)[98k]
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Evaluating Register File Size in ASIP Design,
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel,
M.Balakrishnan,
International Symposium on Hardware Software Codesign
(CODES-2001), Copenhagen, Denmark, pp. 109-114, April 2001.
PDF(gzipped)[124k]
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Exploring Design Space of Parallel Realizations: MPEG-2
Decoder Case Study,
Basant K. Dwivedi, Jan Hoogerbrugge, Paul Stravers and M. Balakrishnan,
International Symposium on Hardware Software Codesign
(CODES-2001), Copenhagen, Denmark, pp. 92-97, April 2001.
PS(gzipped)[60k]
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Efficient Embedding of Partitioned Circuits onto
Multi-FPGA Boards,
S. C. Jain, Anshul Kumar and Shashi Kumar,
FPL 2000, pp. 201-210.
-
Evaluation of Various Routing Architectures for Multi-FPGA
Boards,
S. C. Jain, Shashi Kumar and Anshul Kumar,
13th International Conference on VLSI Design (VLSI-2000),
Calcutta, India, Jan. 2000.
PS(gzipped)[54k]
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Interface Synthesis: Issues and Approaches,
Arvind Rajawat, M. Balakrishnan and Anshul Kumar,
13th International Conference on VLSI Design (VLSI-2000),
Calcutta, India, pp. 92-97, Jan. 2000.
PS(gzipped)[30k]
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Processor Evaluation in an Embedded Systems Design
Environment,
Vinod Gupta, Purvesh Sharma, M. Balakrishnan and Sharad Malik,
13th International Conference on VLSI Design (VLSI-2000),
Calcutta, India, pp. 98-103, Jan. 2000.
PS(gzipped)[26k]
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Optimal Hardware/Software Partitioning for Concurrent
Specification using Dynamic Programming,
Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar and M.
Balakrishnan,
13th International Conference on VLSI Design (VLSI-2000),
Calcutta, India, pp. 110-113, Jan. 2000.
PS(gzipped)[26k]
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Design of Embedded Systems for Real-Time Vision,
Vivek Haldar, Gokul Varadhan, Abhishek Saxena, M. Balakrishnan and
Subhashis Banerjee,
Indian Conf. on Computer Vision, Graphics and Image
Processing (ICVGIP'2000), Bangalore, India, Dec. 2000.
PS(gzipped)[133k]
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Speeding up Power Estimation of Embedded Software,
Akshaye Sama, M. Balakrishnan and J. F. M. Theeuwen,
ISLPED 2000, Italy, pp. 191-196, July 2000.
PS(gzipped)[47k]
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Allocation of FIFO Structures in RTL Data Paths,
M. Balakrishnan and Heman Khanna,
ACM Trans. on Design Automation of Electronis Systems
(TODAES), pp. 294-310, July 2000.
PS(gzipped)[87k]
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