Previous Years Projects

Projects Carried Out in 2006-2007

Design of co-processor for speeding up Drug Design Algorithms

Multicore Emulator on FPGA

Automated design of wrappers for platform FPGAs

Speedup of SONAR application using Multiprocessor Synthesis

Build a system using multiple microblaze soft cores

Exploaring Memory Hierarchy on Microblaze for Xilinx FPGA

Design of SHWS sensor processor

Validation Infrastructure/Tool for Static and Dynamic Validation of Library (Timing Library)

Power modeling for instruction set extention VLIW processor

Matching functionally Equivalent AFU patterns in synthesis of VLIW ASIPs

Projects Carried Out in 2005-2006

Low power behavioral transformation

Power Estimation of FPGA Componants

Low power processor Architectures

Cache Compression

Scheduling and register allocation with coarse grain function units

Unified architecture description for SRIJAN RISC/VLIW

Architecture design space exploration for Application Specific Functional Units

Code generation for clustered VLIW

Target Tracking and Detection

Architecture Specific Behaviour Transformation

Cradle Multi-processor Case Study and Performance Estimation

Projects Carried Out in 2004-2005

Integrated Power Management System for Battery Powered Embedded Systems

Hardware Accerlator for Ray Tracer

Exploration of Cache Architectures

Power Driven Architecture Exploration

Exploring Synthesis for MP using Probablistic methods.

Loop Unrolling Optimizations

FPGA based Network Hardware Lock

Extending and porting rtker to 8051 microcontroller

Projects Carried Out in 2003-2004

Component Library for Embedded Multiprocessor Simulator

A Compiler Optimization to Exploit Pipeline Registers and Forwarding Circuitry

Binary Utilities for Multiprocessor Code Generation

Extensions to Real Time Kernel RtKer

Customization of Cache Memory for Embedded Systems

Power Library of Architectural Components for ASIPs

Process Network Implementation of MPEG4

Bit-width Analysis in Behavioral Synthesis from C

Loop Unrolling Optimizations in Behavioural Synthesis from C

FSM Derivation From SystemC

Floating Point Unit (FPU) Integration with LEON

Hardware Accelerator for Ray-Tracing

LipSync

Hardware-Software Codesign of Text to Speech Synthesizer

Case Study on ADM-XRC2 FPGA Board

Customization of Xtensa Microprocessors

MIPS Emulator

Projects Carried Out in 2002-2003

A Parameterized VLIW ASIP Simulator in SystemC

Memory Optimizations in H/W Synthesizer

Pipelined and Multiple Co-Proc Generation

Architecture Model Refinement and Generation Using SystemC

Multithreaded Real Time Vision Application Modeling

Synthesis and case studies using LEON multiprocessor on FPGAs

Integration of network interface with LEON processor

Extending and porting RtKer to Leon multiprocessor system

Next generation arhictectures (Independent Study)

Hardware Estimation

A Compiler Back-end for A Clustered VLIW Architecture (Best M.Tech Project Award)

Multiprocessor Prototype Using LEON as Building Block

Exploring VLIW ASIP Design Space using Trimaran Based Framework

Specification and Simulation of VLIW Processors with Encoded Instructions

Software Estimation for Multiprocessors

Mapping of Collision Detection Algorithm on Pentium and FPGA Platforms

Case studies using MPEG-Decoder application and LEON Processor

Projects Carried Out in 2001-2002

Performance Evaluation for System Level Design Space Exploration

Hardware Estimation

RTEMS (OS and Applications)

Integration of Tools and Software Estimation

Hardware Synthesis from C

FU Modelling in Trimaran for VLIW ASIPs

Communication Cost Estimation

Projects Carried Out in 2000-2001

Real time kernel synthesis

ASIP Synthesis

Framework for Embedded Systems Synthesis

Case study - JPEG encoder and decoder

Case Study II - FPGA's v/s Pentium, Partitioning of Vision Algorithm on FPGA's and Pentium

Software Estimation

Hardware Estimation

Partitioning

Projects Carried Out till 2000

Visualization of Platforms

http://embedded.cse.iitd.ernet.in