Assignment 5
Exception Handling in BlockSim
For exception handling assignments, you are suppose to do the following-
- Find the exception, using logic gates
- Change PC address to exception sub routine address.
Hint: Use component - Dmux, for providing control for address change
- Exception sub-routine should be written in program file
such that it display, which instruction caused the exception and what
was the instruction address.
- ALU exception people, use this ALU.java and replace with the original one. It should work. Basic difference with the original one is, how it deals with negative numbers
Exception handling Subroutine
- Two registers need to be designed $EPC and $INETR in the processor, EPC contain the address
of the instruction that caused exception, $INETR contains the instruction that caused the
interrupt.
- Following instruction need to be executed in interrupt sub routine
ISR:
mfc0 $t0, $EPC #move $EPC to $t0
lw $t0, 0($t0) #store data at address $t0 at $t0
mtc0 $t0, $INETR #copy $t0 to register $INETR
eret #jump back to next instruction, where exception occurred
- These three instruction (mfc0, mtc0, eret) need to be implemented in designed processor
For Memory Parity Exception
Parity bit can be stored in a different memory file (As
we are constrained with 32 bit width of memory) Address X of memory
file contains the data while address X of parity memory contain
parity bit corresponding to data at X address. While loading data
(using load instruction), this
Input/Output
Input output will be shown in saperate registers, which can be checked during
simulation. For input devices, input will be given by hand (simulator support
giving input to any register by hand during simulation). If you need to model
ready signal that also can be modeled as registers whose input will be given
by hand.
Polled Input
Hardware Part
- Input device will have a ready signal which can be read from
address A1, Data from input device will be available at address A2.
- Connection of the input device would be such that when address
is pointing for an input-output address space, memory will be disabled.
- Address bus to I/O device need to be multiplexed with memory.
Same will be the case of data bus. State of mux will be defined by
the address itself. For example, memory range is 0x0000 to 0x7FFF
and I/O address range is defined by 0x8000 to 0xFFFF or such similar
partition can define address space. For such address space partition,
upper bits of address can be used to determine which device need
to be accessed.
Software Part
- A loop is written in program to be executed, which will read A1
repeatedly. When value at A1 is found one then A2 will be read.
- In loop there will be two instruction, one will be reading the
status of I/O device. Status is read by load instruction, by giving
A1 in address field. Next instruction will check the status. If status
is read then next instruction is issued which will read or write
data at address A2. Again A2 is given as address of load/store
instruction
Polled Output
Polled Output is similar to polled input, except status is read
at address A1, and output is written at address A2.
The loops and structure would be similar to polled input case.
Interrupt driven I/O
- Interrupt is checked at the end of each instruction
- If interrupt is there, PC will be changed to interrupt service routine.
- Interrupt routine will read I/O using load store instructions
Cache
- Students are suppose to design a direct map cache. The cache is
unified as it contain both data and instructions. Each block of the
cache will be of 4 words ( 16 bytes)
- Cache can be implemented using two memory modules, one
containing tags and another containing data array. Tag array will
stores tag and valid bit
- For each load/store instruction, address is compared with the tags,
if address is found in tag array, and valid bit is one, then it is
considered as a hit and corresponding data is stored in the registers.
Note that, tag array and data array can be read simultaneously.
Only if tag matched then data will be used otherwise discarded.
- In case of miss, block is read from main memory. Maim memory is
another memory module which contain all the data. Reading from main
memory assumes that first word is read in 4 cycles and consecutive words
are accessed in one cycle each. Thus for a block of 4 words, it take
7 cycles.
- For writing a suitable policy can be chosen.
- All these will be implemented using control description by increasing the stated of memory operations.
- Memory modules of the simulator take width of the word
as input. For depth it assumes infinite depth. This feature should be used
carefully while designing the cache system