Sr. Project Engineer
Block II- A, Room No-505
Hauz Khas, New Delhi-110016.
I joined the Department of Computer Science and Engineering, IIT Delhi as a PhD student in July 2010. I have submitted my Doctoral Thesis under the guidance of Prof. Preeti Ranjan Panda. From July 2014 onwards, I am working as a senior project engineer with him.
I received Masters Degree in VLSI Design (2008-2010) from Malaviya National Institute of Technology, Jaipur. I also hold a Bachelors (2003-06) and Masters degree (2006-08) in Electronics from University of Delhi, South Campus.
· 2013-14 : I Semester : CSL-728 (Compiler Design) Course Coordinator : Prof. Preeti Ranjan Panda
· 2012-13 : II Semester : CSL-812 (System Level Design and Modeling) Course Coordinator : Prof. Preeti Ranjan Panda
· 2012-13 : II Semester : CSV-881 (Special Topics in Hardware Systems) Course Coordinator : Prof. Kolin Paul
· 2012-13 : I Semester : CSL-728 (Compiler Design) Course Coordinator : Prof. Preeti Ranjan Panda
· 2011-12 : I Semester : CSL-719 (Synthesis of Digital Systems) Course Coordinator : Prof. Anshul Kumar
Embedded Systems Design, Low Power Design, Modeling and Estimation, High Level Synthesis, Device Modeling
· Power Optimization Techniques for DDR3 SDRAM, Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, and Dipankar Sarma, VLSI Design 2015.
· High Level Energy Modeling of Controller Logic in Data Caches, Preeti Ranjan Panda, Sourav Roy, Srikanth Chandrasekaran, Namita Sharma, Jasleen Kaur, Sarath Kumar Kandalam, and Nagaraj N. , GLSVLSI 2014.
· Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition, Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, and Francky Catthoor, DATE 2014.
· Energy Optimization in Android Applications through Wakelock Placement, Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, and Sanjiv Narayan, DATE 2014.
· Array Scalarization in High Level Synthesis, Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, and Ashok Jagannathan, ASP-DAC 2014.
· Data Memory Optimization in LTE Downlink, Namita Sharma, Tom Vander Aa, Prashant Agrawal, Praveen Raghavan, Preeti Ranjan Panda, and Francky Catthoor, ICASSP 2013.
· Early Exploration for Platform Architecture Instantiation with Multi-mode Application Partitioning, Prashant Agrawal, Praveen Raghavan, Matthias Hartmann, Namita Sharma, Liesbet Van der Perre, and Francky Catthoor, DAC 2013. Awarded the HiPEAC paper award.
· Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation, Namita Sharma, Vineet Sahula, and C.P. Ravikumar, IJASCSE 2012.
· Two-Dimensional Analytical Device Modeling of a Novel Multi-Layered Four-Gate MOSFET–A Novel Design, N.Sharma, R.S.Gupta, J.Bansal, R.Chaujar, and M.Gupta, MICROWAVE 2008.
· Two-Dimensional Analytical Sub-threshold model of double gate MOSFET with gate stack, J.Bansal, N.Sharma, R.Chaujar, M.Gupta, and R.S.Gupta, MICROWAVE 2008.
· Analytical Modeling of Multi-Layered dielectric four Gate MOSFET for improved short channel effects, N.Sharma, J.Bansal, S.P.Kumar, R.Chaujar, M.Gupta, and R.S. Gupta, MATEIT 2008.