Assignment 1 ( Single Issue Pipeline Processor)
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Objective :
To understand pipeline stall and branch prediction in single issue machine
and use of simplescalar simulator
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a) Choose 3 benchmarks which are simple and
contain some branches (benchmarks you can
download from www.cse.iitd.ac.in/~asahu/
or moodle courseware )
b) Configure the simulator for single
issue and very large cache such that stalls due to cache
misses don't appear (compulsory misses cannot be avoided).
Part (A)
Estimate number of
cycles taken by your benchmark to execute ignoring delays
introduced
because of pipeline stalls and compare this against number of
cycles given by the simulator. The
difference will give you delay
due to pipeline stalls. (In this case configure the simulator some static
branch prediction)
Part (B)
a)Profile your application using
sim-profile and find out branch probabilities. Also find branch
prediction hit and miss probabilities for your strategy and BTB
hit and miss probabilities.
b)By making use of pipeline
template of the architecture, find out delays at each leaf of the BTB
outcome tree (refer chapter 4 of Flynn's book). Now find out
expected branch delay for your branch
prediction strategy. You should also justify your estimations against
simulation results
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Note for compilation:
* sslittle-na-sstrix-gcc
cannot compile // type commenting style in the C program. So you will
have
to change the commenting style in the source program to /* --- */
style.
* Don't use makefiles given in the benchmarks set as
there target machine is existing DSP machines.
Since, these applications are very small, you may not require a
makefile at all. You may also need to remove
one/two macros such as "BEGIN PROFILING" and "END PROFILING" in dsptone
applications.
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Submission procedure: The assignment submission
must contain the following:
* Writeup on the exercise with the help of pipeline
template diagrams for different branches in your benchmark
and anlaysis. The
writeup should be in pdf format.
* The softcopy of your benchmarks in C and
simplescalar assembly form and input data set.
* The softcopy of output dataset.
All the above thing must be compressed(.zip/.tgz/.bz2/.tar.gz)
and submit through moodle
courseware
(http://megh.cse.iitd.ac.in/moodle/).
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Deadline: 31th Jan 2006 (
Tuesday)
Note that any late submission is subjected to degradation. For late
submission of each day 1/10th of the wightage
of assignment will be deducted. Any submission after one week
will be rejected.
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Demo: Always Demo schedules will be announced just 1
day after the deadlines of submission and venue of
demo will be in Architecture Lab, 4th floor, Bharti Building.
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Further any clarification: emailto:asahu@cse.iitd.ac.in